A ddr processing circuit based on fpga and its realization method

Abstract

The invention provides an FPGA-based DDR processing circuit and a realization method. The processing circuit comprises a DDR interface, a delay module connected with the DDR interface, a DDR input register module connected with the DDR interface, a clock switching module connected with the delay module, a first FIFO module and a second FIFO module which are connected with the DDR input register module, a user clock module connected with the clock switching module and an output switching module connected with the first FIFO module and the second FIFO module; the clock switching module is also connected with the first FIFO module and the second FIFO module; the user clock module is also connected with the output switching module, the first FIFO module and the second FIFO module; and the delay module is also connected with the DDR input register module. According to the FPGA-based DDR processing circuit, the DDR interface is converted into a general FIFO interface, the design demand of an FPGA is met, and the FPGA-based DDR processing circuit is quite convenient and easy to use.

Description

technical field [0001] The invention belongs to the field of circuit design, and in particular relates to an FPGA-based DDR processing circuit and an implementation method. Background technique [0002] In recent years, with the continuous acceleration of data transmission speed, the traditional effective data transmission method at the rising edge of the clock can no longer meet the needs of some high-performance read and write. In order to solve this problem, people have proposed the DDR interface. The DDR interface means that the data is valid on both the upper and lower edges of the clock, so that the transmission speed is twice that of the data on the rising edge. As an important electronic device in the modern electronic field, FPGA's The design generally follows the principle of rising edge synchronization, and cannot directly use the DDR transmission method. [0003] This is the deficiency of the prior art. Therefore, it is very necessary to provide an FPGA-based DD...

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Problems solved by technology

[0004] The object of the present invention is to, aim at the defective that above-mentioned FPGA can not directly use DDR transmission mode, provide a kind of DDR processing circuit and implementation method based on FPGA, to solve above-mentioned technical problem

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