Efficient Work Execution In A Parallel Computing System

A technology of computing equipment and computing methods, applied in computing, program control design, instruments, etc., can solve the problems of inflexible allocation of work groups, unsuitable for specific data access modes, etc., and achieve the effect of efficient data access

Active Publication Date: 2017-10-03
MEDIATEK INC
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

However, traditional hardware platforms are not suitable for certain cores with specific data access patterns, and are not flexible for the assignment of workgroups

Method used

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  • Efficient Work Execution In A Parallel Computing System
  • Efficient Work Execution In A Parallel Computing System
  • Efficient Work Execution In A Parallel Computing System

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Embodiment Construction

[0022] Certain terms are used throughout the description and claims to refer to particular components. It should be understood by those skilled in the art that manufacturers may use different terms to refer to the same component. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of components as a basis for distinction. The "comprising" mentioned throughout the specification and claims is an open term, so it should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described that the first device is coupled to the second device, it means that the first device may be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0023] A recurring computational problem in signal a...

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Abstract

A computing device performs parallel computations using a set of thread processing units and a memory shuffle engine. The memory shuffle engine includes a register array to store an array of data elements retrieved from a memory buffer, and an array of input selectors. According to a first control signal, each input selector transfers at least a first data element from a corresponding subset of the register array, which is coupled to the input selector via input lines, to one or more corresponding thread processing units. According to a second control signal, each input selector transfers at least a second data element from another subset of the register array, which is coupled to another input selector via other input lines, to the one or more corresponding thread processing units.

Description

[0001] 【cross reference】 [0002] This application claims the priority of the U.S. Provisional Application No. 62 / 312,567 filed on March 24, 2016, and the content of the above provisional application is incorporated into this application. 【Technical field】 [0003] Embodiments of the present invention relate to a parallel computing device (parallel computing device) and a computing method executed by the parallel computing device. 【Background technique】 [0004] Parallel computing has been widely implemented in modern computing systems. To support efficient parallel computing, several parallel programming models have been developed for programmers to write code that executes across heterogeneous platforms; for example, such platforms may include central processing units (CPUs), graphics processing units (GPUs), A combination of digital signal processors (DSPs), field programmable gate arrays (FPGAs), hardware accelerators, etc. Commonly used parallel programming models inc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/44G06F9/38
CPCG06F8/35G06F9/3836G06F9/3824G06F9/383G06F9/3851G06F9/3887
Inventor 赖守仁丛培贵范博钧蔡松芳
Owner MEDIATEK INC
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