Test structure, preparation method and test method for short-circuit defect of shared contact hole
A technology for sharing contact holes and short-circuit defects, which is applied in semiconductor/solid-state device testing/measurement, circuits, electrical components, etc., and can solve the problems of inaccuracy in optical inspection, failure of electrical defects, monitoring, etc.
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[0040] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.
[0041] The following is attached Figure 6-10 The present invention will be described in further detail with specific examples. It should be noted that the drawings are all in a very simplified form, using imprecise scales, and are only used to facilitate and clearly achieve the purpose of assisting in describing the present embodiment.
[0042] see Figure 6 and Figure 8 , a test structure for a short-circuit defect in a gate-source shared contact hole in this embodiment has a transistor of the first conductivity type, which is a PMOS transistor here. In this...
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