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De-serialization circuit and method of operating the same

A deserialization and circuit technology, applied in parallel/serial conversion, electrical components, generating electrical pulses, etc., can solve problems affecting IC performance and IC complexity

Active Publication Date: 2017-10-31
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As ICs become smaller and more complex, the clock generation frequency of these electronic devices continues to affect the performance of ICs

Method used

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  • De-serialization circuit and method of operating the same
  • De-serialization circuit and method of operating the same
  • De-serialization circuit and method of operating the same

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Embodiment Construction

[0019] The following disclosure provides various embodiments, or examples, for implementing features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, a first functional part formed on or over a second functional part may include an embodiment in which the first functional part and the second functional part are formed in direct contact, and may also include an embodiment in which the first functional part and the second functional part are formed in direct contact. An embodiment in which an additional functional component is formed between two functional components so that the first functional component and the second functional component cannot be directly contacted. Furthermore, the present invention may repeat reference numerals and / or letters in various examples...

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Abstract

A de-serialization circuit includes a clock generation circuit, a first and a second latch circuit. The clock generation circuit is configured to generate a set of phase clock signals based on a first clock signal and a control signal. Each phase clock signal of the set of phase clock signals being offset from adjacent phase clock signals of the set of phase clock signals by a phase value. The first latch circuit is configured to generate a first set of data signals based on the set of phase clock signals and an input data signal. The second latch circuit is configured to generate a second set of data signals based on a first phase clock signal of the set of phase clock signals and the first set of data signals. Each signal of the second set of data signals being aligned with each other, wherein the first clock signal is non-continuous. The invention also provides a method of operating the de-serialization circuit.

Description

technical field [0001] Embodiments of the present invention generally relate to the field of semiconductor technology, and more particularly, to deserialization circuits and methods of operation thereof. Background technique [0002] The semiconductor integrated circuit (IC) industry has produced a wide variety of electronic devices to solve problems in different fields. As ICs become smaller and more complex, the clock generation frequency of these electronic devices continues to affect the performance of the ICs. Contents of the invention [0003] According to an aspect of the present invention, there is provided 1. A deserialization circuit, comprising: a clock generation circuit configured to generate a phase clock signal group based on a first clock signal and a control signal, each of the phase clock signal groups The offset between the phase clock signal and the adjacent phase clock signals of the phase clock signal group is a phase value; the first latch circuit i...

Claims

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Application Information

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IPC IPC(8): H03M9/00
CPCH03M9/00H03K5/15013H03K21/026H03K3/037
Inventor 李绍宇
Owner TAIWAN SEMICON MFG CO LTD