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Shift register unit, driving method thereof and display panel

A shift register unit and driver technology, applied in information storage, static memory, static indicators, etc., can solve problems such as output instability

Active Publication Date: 2017-11-03
WUHAN TIANMA MICRO ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Embodiments of the present invention provide a shift register unit, its driving method, and a display panel to solve the problem of unstable output in the prior art

Method used

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  • Shift register unit, driving method thereof and display panel
  • Shift register unit, driving method thereof and display panel
  • Shift register unit, driving method thereof and display panel

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0108] by Figure 5a to Figure 5c Take the shift register unit shown as an example, all transistors in the shift register unit are P-type transistors, and the corresponding input and output timings are as follows: Figure 8a as shown, Figure 8a An input and output timing diagram corresponding to the shift register unit provided by the embodiment of the present invention; specifically, select as Figure 8a P1, P2, P3, P4, P5, P6, P7 and P8 eight stages in the input timing diagram shown.

[0109] In the P1 stage, STV=1, CK1=0, CK2=1, CK3=1.

[0110] Since STV=1, the first transistor T1 is turned off. Since CK2=1, the eighth transistor T8 is turned off. Since CK3=1, the second transistor T2 is turned off. Due to the action of the second capacitor C2, the potential of the second node N2 remains high, and the third transistor T3 is turned off. Under the action of the third capacitor C3, the first node N1 maintains the low potential of the previous stage. The sixth transisto...

example 2

[0127] by Figure 6a to Figure 6c Take the shift register unit shown as an example, all transistors in the shift register unit are P-type transistors, and the corresponding input and output timings are as follows: Figure 8a as shown, Figure 8a An input and output timing diagram corresponding to the shift register unit provided by the embodiment of the present invention; specifically, select as Figure 8a P1, P2, P3, P4, P5, P6, P7 and P8 eight stages in the input timing diagram shown.

[0128] In the P1 stage, STV=1, CK1=0, CK2=1, CK3=1.

[0129] In this stage, the tenth transistor T10 is turned off under the control of the third node N3. The working process of the shift register unit is the same as that of the P1 stage in Example 1, and will not be repeated here.

[0130] In the P2 stage, STV=1, CK1=1, CK2=0, CK3=1.

[0131] In this stage, the tenth transistor T10 is turned off under the control of the third node N3. The working process of the shift register unit is t...

example 3

[0146] by Figure 7a to Figure 7c Take the shift register unit shown as an example, all transistors in the shift register unit are N-type transistors, and the corresponding input and output timing is as follows Figure 8b as shown, Figure 8b Another input and output timing diagram corresponding to the shift register unit provided by the embodiment of the present invention; specifically, select as Figure 8b P1, P2, P3, P4, P5, P6, P7 and P8 eight stages in the input timing diagram shown.

[0147] In the P1 stage, STV=0, CK1=1, CK2=0, CK3=0.

[0148] Since STV=0, the first transistor T1 is turned off. Since CK2=0, the eighth transistor T8 is turned off. Since CK3=0, the second transistor T2 is turned off. Due to the action of the second capacitor C2, the potential of the second node N2 remains low, and the third transistor T3 is turned off. Under the action of the third capacitor C3, the first node N1 maintains the high potential of the previous stage. The sixth transis...

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Abstract

The invention discloses a shift register unit, a driving method thereof and a display panel. The shift register unit comprises an output module, a first driver, a second driver and a feedback adjustment module, wherein the output module is used for providing signals at a first signal end or a second signal end to an output end according to voltage applying to a first node and a third node; the first driver is used for controlling voltage of the first node and a second node according to signals of a first input end and a second input end; the second driver is used for controlling the voltage of the third node according to the voltage of the first node and the second node; and the feedback adjustment module is used for controlling voltage of the first node according to signals at the output end, a third input end and a fourth input end. As the feedback adjustment module can control the first node according to the output end, the potential of the first node can be stabilized better, and the circuit output can be more stable.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a shift register unit, its driving method and a display panel. Background technique [0002] With the continuous development of display screens, consumers have higher and higher requirements for the stability of display screens. The stability of the display screen is largely reflected in the gate drive circuit and the shift register unit forming the gate drive circuit. [0003] Currently, the shift register unit mostly adopts a 5T2C structure (that is, includes 5 switching transistors and 2 capacitors). Such as Figure 1a as shown, Figure 1a A schematic structural diagram of a shift register unit provided in the prior art; the first switching transistor M1 to the fifth switching transistor M5 are all P-type thin film transistors. Such as Figure 1b shown in the circuit timing diagram, Figure 1b for Figure 1a The circuit timing diagram corresponding to the shift register ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/20G11C19/28
CPCG09G3/20G11C19/28G09G2310/0286G11C19/184G09G3/3677G09G5/003
Inventor 李玥朱仁远向东旭蔡中兰朱娟
Owner WUHAN TIANMA MICRO ELECTRONICS CO LTD
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