A Superjunction MOSFET Device with Guard Ring
A protection ring and device technology, applied in semiconductor devices, electrical components, transistors, etc., can solve problems such as device failure, improve reliability, avoid parasitic transistors from turning on, and improve the ability to resist UIS failure.
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Embodiment 1
[0024] Such as figure 1As shown, this embodiment provides a super junction MOSFET device with a guard ring, which is characterized in that its active region has at least one cell array formed by several cells and surrounding the cell array The combined unit formed by the guard ring, the structure of any unit cell includes a metallized drain 1, a first conductivity type semiconductor doped substrate 2, a first conductivity type semiconductor doped epitaxial region 3, a second conductivity type semiconductor from bottom to top. Type semiconductor doped body region one 6, gate and metallized source 11, wherein: the second conductivity type semiconductor doped column region 4 arranged at intervals in the first conductivity type semiconductor doped epitaxial region 3 forms a super junction structure; the lower surface of the second conductivity type semiconductor doped column region 4 coincides with the upper surface of the first conductivity type semiconductor doped substrate 2; t...
Embodiment 2
[0030] The structure of the present invention is the same as that of Embodiment 1 except that the width of the second conductivity type semiconductor ring region 5 is greater than the width of the second conductivity type semiconductor column region 4 .
[0031] Based on the above description of the principle, it can be deduced that increasing the charge imbalance in the semiconductor ring region 5 of the second conductivity type is beneficial to fix the avalanche breakdown point.
[0032] In the above embodiments, the present invention does not limit the number of cells, and the number of cells in the cell array surrounded by the guard ring structure is defined as n (n≧1), and the value of n can be determined according to the required on-resistance of the device. and current capability are designed.
[0033] In the above embodiments, the present invention does not limit the number of combination units composed of a cell array and a guard ring structure surrounding the cell ar...
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