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A Superjunction DMOS Device with High Avalanche Capability

An avalanche tolerance and device technology, applied in semiconductor devices, electrical components, circuits, etc., can solve problems such as reducing parasitic BJT base resistance, increasing the threshold voltage of DMOS devices, and unable to completely prevent parasitic BJT transistors from turning on, so as to improve device performance. The effect of reliability

Inactive Publication Date: 2019-09-13
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Similarly, such a solution still cannot completely eliminate the opening of the parasitic BJT tube, and it cannot completely avoid the device failure problem caused by avalanche breakdown; in addition, it cannot reduce the power DMOS through high-energy boron implantation or deep diffusion. The resistance of the P-body region under the N+ source region can be used to infinitely reduce the parasitic BJT base region resistance, because this will increase the threshold voltage (channel turn-on voltage) of the DMOS device

Method used

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  • A Superjunction DMOS Device with High Avalanche Capability
  • A Superjunction DMOS Device with High Avalanche Capability
  • A Superjunction DMOS Device with High Avalanche Capability

Examples

Experimental program
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Embodiment 1

[0022] A high avalanche withstand superjunction DMOS device, such as figure 2 As shown, from bottom to top, it includes metallized drain electrode 1, first conductivity type semiconductor doped substrate 2, first conductivity type semiconductor doped column region 3, second conductivity type semiconductor doped column region 6, polysilicon gate An electrode 10, a gate dielectric layer 11, and a metallized source electrode 12. The second conductivity type semiconductor doped column region 6 is located on both sides of the first conductivity type doped column 3; the top of the first conductivity type doped column 3 has a first conductivity type doped region 35 with a lower doping concentration, the first The bottom of the conductive type doped column 3 has a first conductive type doped region 34 with a lower doping concentration; the top of the second conductive type semiconductor doped column region 6 has a second conductive type semiconductor body region 7, and the second cond...

Embodiment 2

[0028] As shown in FIG. 7 , the structure of this example is based on the example 2, and the doped column 3 of the first conductivity type only has a low-doped first conductivity type doped region 35 at the top. The low-doped first conductivity type doped region 35 can reduce the electric field at the second conductivity type semiconductor body region 7, which can effectively avoid the avalanche current from the base resistance of the parasitic BJT, and improve the device in the non-clamp bit reliability in inductive load applications.

Embodiment 3

[0030] like Figure 8 As shown, the structure of this example is based on Example 2, and the doped column 3 of the first conductivity type only has a low-doped first conductivity type doped region 34 at the bottom. The low-doped first conductivity type doped region 34 can increase the electric field at the lower part of the second conductivity type semiconductor doped column region 6, which can effectively avoid the avalanche current from the base resistance of the parasitic BJT, and improve the performance of the device. reliability in unclamped inductive load applications.

[0031] In the above embodiments, silicon carbide, gallium arsenide, silicon germanium and other semiconductor materials can also be used instead of silicon when making devices.

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Abstract

The invention relates to the technical field of power semiconductor devices, in particular to a super junction DMOS (double diffusion metal-oxide-semiconductor) device with high avalanche tolerance. On the basis of the conventional super junction DMOS device, doping concentration of a first conduction type doping column region of a super junction structure is changed to fix the avalanche breakdown point of the super junction DMOS device, to be specific, the doping concentration of the upper portion of the first conduction type doping column region of the super junction structure is reduced to reduce intensity of an electric field nearby a second conduction type semiconductor body region, and meanwhile, the doping concentration of the lower portion of the first conduction type doping column region of the super junction structure is reduced to increase intensity of an electric field of the bottom part of a second conduction type doping column region. Therefore, the avalanche breakdown current path avoids a base resistance of a parasitic BJT(Bipolar Junction Transistor); starting of a parasitic bipolar transistor is avoided effectively in the avalanche breakdown of the super junction DMOS device, and the reliability, namely UIS failure resistance capacity, of the super junction DMOS device in UIS (unclamped inductive switching ) application is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor power devices, and relates to a super junction DMOS device with high avalanche tolerance. Background technique [0002] Super Junction (SJ) MOSFET breaks the "silicon limit" of conventional power DMOS, and has the characteristics of small on-resistance and low switching loss, and can be widely used in industrial control systems, automotive electronics, consumer electronics, It is a new type of power device that is widely used in the fields of household appliances and aerospace. Solving the reliability problem of super-junction DMOS in system application is a prerequisite for realizing its large-scale application. [0003] The switching process under the unclamped inductive load (Unclamped Inductive Switching, UIS) is generally considered to be the most extreme electrical stress situation that the power DMOS can encounter in the system application. Because the energy stored in the inductor ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06
Inventor 任敏罗蕾谢驰林育赐李佳驹李泽宏张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA