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A super junction dmos device

A device and conductivity type technology, applied in the field of superjunction DMOS devices, can solve the problems of reducing parasitic BJT base resistance, unable to completely eliminate parasitic BJT transistors from turning on, increasing the threshold voltage of DMOS devices, etc., to achieve the effect of improving device reliability.

Inactive Publication Date: 2020-01-17
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Similarly, such a solution still cannot completely eliminate the opening of the parasitic BJT tube, and it cannot completely avoid the device failure problem caused by avalanche breakdown; in addition, it cannot reduce the power DMOS through high-energy boron implantation or deep diffusion. The resistance of the P-body region under the N+ source region can be used to infinitely reduce the parasitic BJT base region resistance, because this will increase the threshold voltage (channel turn-on voltage) of the DMOS device

Method used

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  • A super junction dmos device
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  • A super junction dmos device

Examples

Experimental program
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Effect test

Embodiment 1

[0019] A superjunction DMOS device such as figure 1As shown, it includes a metallized drain electrode 1, a first conductivity type semiconductor doped substrate 2, a first conductivity type doped column region 3, a second conductivity type semiconductor doped column region 4, a polysilicon gate electrode 10, and a gate dielectric layer 11. Metallized source electrode 12. The metallized drain electrode 1 is located on the lower surface of the first conductivity type semiconductor doped substrate 2; the first conductivity type doped column region 3 and the second conductivity type semiconductor doped column region 4 are located on the first conductivity type semiconductor doped substrate 2 Upper surface; there is a low-doped first conductivity type doped region 6 above the first conductivity type doped column region 3; the second conductivity type semiconductor doped column region 4 is located on both sides of the first conductivity type doped column region 3 , and form a super...

Embodiment 2

[0025] like Figure 4 As shown, the structure of this example is based on Example 1, and the two ends of the metallized source electrode 12 described in Example 1 are extended downwards into the semiconductor body region 7 of the second conductivity type to form a trench structure; The second conductivity type semiconductor doped contact region 9 is located at the bottom of the trench with the metallized source electrode 12 at both ends. The structure can further optimize the avalanche current path and improve the UIS capability of the device.

[0026] When making devices, semiconductor materials such as silicon carbide, gallium arsenide, or silicon germanium can also be used instead of silicon.

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Abstract

The invention provides a super junction DMOS device. An avalanche breakdown point of the super junction DMOS device is fixed by making a medium layer structure on the lateral surface of a second conduction type doped column region of a super junction structure, and meanwhile, doping concentration of the top of the second conduction type doped column region of the super junction structure is reduced, so that an electric field near a second conduction type semiconductor body region is reduced. Finally, an avalanche breakdown current path avoids a base resistance of a parasitic BJT (Bipolar Junction Transistor), and when avalanche breakdown occurs to the super junction DMOS device, turn-on of the parasitic transistor is effectively avoided, so that reliability (i.e., resistance to UIS (Unclamped Inductive Switching) failure) of the super junction DMOS device in non-clamping inductive load application is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor power devices, and relates to a super junction DMOS device. Background technique [0002] Power DMOS plays an important role in power conversion, especially in high-frequency power conversion, because of its advantages such as fast switching speed, low loss, high input impedance, low driving power, and good frequency characteristics. Continuously improving system performance requires power DMOS with lower power loss and higher reliability under high electrical stress. When there is an unclamped inductive load in the system loop, the energy stored in the inductor in the on state will be released by the DMOS when it is turned off, and high voltage and high current will be applied to the power DMOS at the same time, which will easily cause device failure . Therefore, the anti-UIS (Unclamped Inductive Switching, unclamped inductive switching process) failure capability is generally considered ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06
CPCH01L29/0615H01L29/0684H01L29/7801
Inventor 任敏罗蕾李佳驹谢驰林育赐李泽宏张波
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA