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A Superjunction vdmos Device with Variable Bandgap

A bandgap width and device technology, applied in the field of super-junction VDMOS devices, can solve the problems of increasing the threshold voltage of VDMOS devices, reducing the parasitic BJT base resistance, and unable to completely prevent the parasitic BJT tube from being turned on, so as to improve the reliability of the device Effect

Active Publication Date: 2020-03-17
HANGZHOU SILICON-MAGIC SEMICON TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Similarly, such a solution still cannot completely eliminate the opening of the parasitic BJT tube, and it cannot completely avoid the device failure problem caused by avalanche breakdown; in addition, it cannot reduce the power VDMOS through high-energy boron implantation or deep diffusion. The resistance of the P-body region under the N+ source region can be used to infinitely reduce the parasitic BJT base region resistance, because this will increase the threshold voltage (channel turn-on voltage) of the VDMOS device

Method used

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  • A Superjunction vdmos Device with Variable Bandgap
  • A Superjunction vdmos Device with Variable Bandgap
  • A Superjunction vdmos Device with Variable Bandgap

Examples

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Embodiment 1

[0024]A super junction VDMOS device with variable bandgap width, comprising a metallized drain electrode 1, a first conductivity type semiconductor doped substrate 2, a first conductivity type doped region 3, a second conductivity type semiconductor doped column region 6, Polysilicon gate electrode 10, gate dielectric layer 11, metallized source electrode 12; metallized drain electrode 1 is located on the lower surface of the first conductivity type semiconductor doped substrate 2; the first conductivity type doped region 3 and the second conductivity type semiconductor doped The miscellaneous column region 6 is located on the upper surface of the first conductivity type semiconductor doped substrate 2; the second conductivity type semiconductor doped column region 6 is located on both sides of the first conductivity type doped region 3, and is connected to the first conductivity type doped region 3 Form a super junction structure; the top of the second conductivity type semico...

Embodiment 2

[0033] Such as Figure 4 As shown, the structure of this example is that on the basis of Example 1, the two ends of the metallized source electrode 12 described in Example 1 are extended downwards into the semiconductor body region 7 of the second conductivity type to form a trench structure; The second conductive type semiconductor doped contact region 9 is located at the bottom of the trench with the metallized source electrode 12 at both ends. The structure can further optimize the avalanche current path and improve the UIS capability of the device.

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Abstract

The present invention provides a superjunction VDMOS device with variable forbidden band width, which includes a metallized drain electrode, a substrate doped with a semiconductor of the first conductivity type, a doped region of the first conductivity type, a column region doped with a semiconductor of the second conductivity type, and polysilicon Gate electrode, gate dielectric layer, metallized source electrode; the present invention introduces a narrow bandgap first conductivity type doping region using a narrow bandgap semiconductor material on the side of the second conductivity type doped column region of a conventional super junction VDMOS device, and A wide bandgap first conductivity type doping region using a wide bandgap semiconductor material is introduced directly above the first conductivity type doping region and the narrow bandgap first conductivity type doping region. Through the above measures, the superjunction can be effectively changed When the avalanche breakdown of the VDMOS device occurs, the avalanche breakdown current path keeps the avalanche breakdown current away from the base region of the parasitic BJT, thereby avoiding the forward bias of the emitter of the parasitic BJT and causing the BJT to turn on, thereby improving the reliability of the device.

Description

technical field [0001] The invention belongs to the technical field of semiconductor power devices, and relates to a super junction VDMOS device with variable forbidden band width. Background technique [0002] Power VDMOS plays an important role in power conversion, especially in high-frequency power conversion, because of its advantages such as fast switching speed, low loss, high input impedance, low driving power, and good frequency characteristics. Continuously improving system performance requires power VDMOS with lower power loss and higher reliability under high electrical stress. When there is an unclamped inductive load in the system loop, the energy stored in the inductance in the on state will be released by the VDMOS when it is turned off, and high voltage and high current will be applied to the power VDMOS at the same time, which will easily cause device failure . Therefore, the anti-UIS (Unclamped Inductive Switching, unclamped inductive switching process) f...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/336H01L29/78
CPCH01L29/0634H01L29/66712H01L29/7802
Inventor 李泽宏罗蕾谢驰李佳驹张金平任敏高巍张波
Owner HANGZHOU SILICON-MAGIC SEMICON TECH CO LTD