Driving circuit and liquid crystal display device
A technology of drive circuit and gate drive circuit, which is applied to static indicators, instruments, etc., can solve the problems of constant power consumption for display and cannot meet the requirements of low power consumption of liquid crystal displays, and achieve the effect of saving power consumption
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no. 1 example
[0031] Such as figure 2 Shown is a schematic structural diagram of the driving circuit of the first embodiment of the present invention. Such as figure 2 As shown, the driving circuit provided by the present invention is used to drive the display panel 101 . The driving circuit includes a timing controller 110 , a gate driving circuit 120 and a source driving circuit 130 .
[0032] Wherein, the timing controller 110 is used for outputting the gate timing signal to the gate driving circuit 120 , and outputting the source timing signal to the source driving circuit 130 .
[0033] The gate drive circuit 120 includes a plurality of sub-gate drive circuits arranged in sequence, and each sub-gate drive circuit includes m gate drive units. Specifically, m may be equal to 3 or 4. In the first embodiment, m is equal to 3, and each The level gate driving unit is used to output the level gate driving signal Gn (n is equal to 1, 2, 3...N) to the corresponding sub-pixel according to t...
no. 2 example
[0060] Such as Figure 9 Shown is a schematic structural diagram of the driving circuit of the second embodiment of the present invention. Such as Figure 9 As shown, the driving circuit provided by the present invention is used to drive the display panel 101 . The driving circuit includes a timing controller 110 , a gate driving circuit 120 and a source driving circuit 130 .
[0061] Wherein, the timing controller 110 is used for outputting the gate timing signal to the gate driving circuit 120 , and outputting the source timing signal to the source driving circuit 130 .
[0062] The gate drive circuit 120 includes a plurality of sub-gate drive circuits arranged in sequence, and each sub-gate drive circuit includes 4 (m is equal to 4) gate drive units, and each level of gate drive units is used to output the current sequence according to the gate timing signal. level gate drive signal Gn (n is equal to 1, 2, 3...N) to the corresponding sub-pixel, wherein, N is an integer g...
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