Chip fan-out packaging structure, multi-chip integrated module and wafer-level packaging method

Abstract

The invention discloses a chip fan-out packaging structure having an antenna, a multichip integrated module and a wafer level packaging method. The antenna is formed in the first groove of a support plate used for accommodating a radio frequency chip and extends to the first surface of the support plate, and then a first metal rewiring layer is formed on the radio frequency chip and the first surface of the support plate so that interconnection between the antenna and the chip can be realized, the function of chip level antenna integration can be achieved without occupying the area of the metal interconnection layer in the chip, and the manufacturing cost can be greatly reduced. According to the multichip integrated module, electromagnetic interference shielding of the functional chip and antenna integration of the radio frequency chip can be simultaneously realized so that the production technology is simple without time consumption, the cost is low without the problems that the surface of the packaging body is rough after packaging and the continuity of the electromagnetic interference shielding structure is difficult to guarantee, and grounding connection can be more easily manufactured in comparison with the conventional method. According to the wafer level packaging method, the method is low in cost and high in efficiency, and the electromagnetic interference shielding structure and the antenna are simultaneously integrated so that the manufacturing cost can be greatly reduced.

Description

technical field [0001] The invention relates to the technical field of fan-out wafer-level packaging, in particular to a chip fan-out packaging structure for an integrated antenna, a multi-chip integrated module and a wafer-level packaging method. Background technique [0002] Fan-out wafer-level packaging is to realize fan-out packaging of chips at the wafer size level. It is also an advanced packaging process with a large number of I / Os and good integration flexibility. It can realize vertical and horizontal multi-chip integration in one package. . As such, fan-out wafer-level packaging is currently being developed into next-generation packaging technologies such as multi-die, low-profile packaging, and 3D SiP. With the development of electronic products in the direction of thinner, lighter, higher pin density, and lower cost, the emergence of fan-out wafer-level packaging technology provides an opportunity for the packaging industry to develop multi-functional small-size...

AI Technical Summary

Problems solved by technology

Because it is a chip-level process, it is time-consuming; and the surface after packaging is rough, it is difficult to ensure the continuity of the conductive layer, and it is also difficult to make the ground connection of the conductive layer

Images