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Storage unit and memory

A technology of storage unit and memory, which is applied in the field of memory, can solve the problems of low reliability and long reading time of storage units, and achieve the effects of large current interval, shortening reading time, and improving reliability

Inactive Publication Date: 2017-12-29
SEMICON MFG INT TIANJIN +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The object of the present invention is to provide a storage unit and a memory to solve the problems of long reading time and low reliability of the storage unit in the prior art

Method used

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Embodiment Construction

[0029] The storage unit and memory of the present invention will be described in more detail below in conjunction with schematic diagrams, wherein a preferred embodiment of the present invention is represented, and it should be understood that those skilled in the art can modify the present invention described here and still realize the beneficial effects of the present invention . Therefore, the following description should be understood as the broad knowledge of those skilled in the art, but not as a limitation of the present invention.

[0030] In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions and constructions are not described in detail since they would obscure the invention with unnecessary detail. It should be appreciated that in the development of any actual embodiment, numerous implementation details must be worked out to achieve the developer's specific goals, such as changing f...

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Abstract

The invention provides a storage unit and a memory. The storage unit comprises a first sub-storage unit and a second sub-storage unit, wherein the first sub-storage unit comprises a first transistor and a second transistor, a gate electrode of the first transistor is connected with a selected gate line, a source electrode of the first transistor is connected with a drain electrode of the second transistor, a drain electrode of the first transistor is connected with a first bit line, a gate electrode of the second transistor is connected with a first word line, and a source electrode of the second transistor is connected with a source line; the second sub-storage unit comprises a third transistor and a fourth transistor, a gate electrode of the third transistor is connected with the selected gate line, a source electrode of the third transistor is connected with a drain electrode of the fourth transistor, a drain electrode of the third transistor is connected with a second bit line, a gate electrode of the fourth transistor is connected with a second word line, and a source electrode of the fourth transistor is connected with the source line; and the first sub-storage unit and the second sub-storage unit are opposite in logic state. In the reading process of the storage unit, a reference current is not needed, the current interval read by the storage unit is larger, reading time is shortened, and reading reliability is improved.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a storage unit and a memory. Background technique [0002] Memory is an important part of digital integrated circuits, and it is an indispensable part of building application systems based on microprocessors. In recent years, various memories have been embedded in the processor to improve the integration and work efficiency of the processor. Therefore, the performance of the memory array and its peripheral circuits largely determines the work efficiency of the entire system. [0003] The read circuit is an important part of the peripheral circuit of the memory. The read circuit is usually used to sample and transform the tiny signal on the bit line (BL, Bit Line) of the memory cell when the memory cell is read. Zoom in to determine the stored information in the storage unit. [0004] The working mechanism of the read circuit is to read the data in the memory cell by comparing th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/12G11C7/10
CPCG11C7/1051G11C7/12
Inventor 叶晓
Owner SEMICON MFG INT TIANJIN