Capacitor array, successive approximation type analog-to-digital converter and capacitor array substrate

Abstract

The invention discloses a capacitor array, a successive approximation type analog-to-digital converter and a capacitor array substrate. The capacitor array for the analog-to-digital converter comprises a control logic generation circuit, a control code logic conversion circuit, and a first sub-capacitor array and a second sub-capacitor array which are used for forming high and low orders. According to the technical scheme provided by the invention, the capacitance of second capacitor cells is set to be equal, so the second capacitor cells in the second sub-capacitor array are correspondingly switched in sequence. No matter a second binary code jumps at which bit, a great number of second capacitor cells are not switched at the same time, so a relatively high conversion error is not caused.According to the technical scheme provide by the invention, in a segmented capacitor array setting mode, the problem that the number of parallel branches is relatively high due to the fact that the second sub-capacitor array is used completely is solved.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuits, in particular to a capacitor array, a successive approximation analog-to-digital converter and a capacitor array board. Background technique [0002] The full name of SAR ADC is successive approximation analog-to-digital converter, which is the most mainstream low-power analog-to-digital converter at present. One of the core modules of SAR ADC, CDAC—digital-to-analog converter capacitor array; SAR ADC, as a key component of the interface between analog modules and digital modules, is widely used in mobile devices, wireless sensors and other devices, due to the size of the device and battery life The problem requires that the analog-to-digital converter has the characteristics of small size and low power consumption, and is easy to integrate in the circuits of various devices. Due to the limitation of the process, the mismatch and error of CDAC are inversely proportional to the ar...

AI Technical Summary

Problems solved by technology

[0004] The impact of CDAC on the conversion accuracy of SAR ADC is mainly reflected in the following ways: when the binary control code of CDAC jumps from 0111111 to 1000000 or from 0011111 to 0100000, in these cases it is only a change of LSB (least significant bit) , but it will cause a large number (2 to the Nth power, N depends on the bit of the jump) switching of unit capacitance, so it will jump from 0111111 to 1000000, X011111 to X100000, XX01111 to XX10000 and similar situations , will lead to a large number of unit capacitance switching, (specifically, 0111111 to 1000000 will cause 127 unit capacitance switching, X011111 to X1000000 will cause 63 unit capacitance switching), and more unit capacitance switching will lead to the introduction of more errors , resulting in non-linearity in the conversion process, resulting in conversion errors, which in turn affect the conversion accuracy of the SAR ADC

[0005] There are currently two main solutions to the mismatch and error of CDAC. One is that engineers can reduce the overall mismatch and error through excellent layout design based on their own experience, but this method cannot essentially change the impact of process error on ADC. The impact of conversion accuracy, so the effect is not obvious; the other is to calibrate through the digital back-end, measure the mismatch and error, and then calibrate the nonlinearity back through the digital back-end. This method is very complicated to implement and requires a lot of energy. digital circuit, and the measurement accuracy is difficult to guarantee

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