Pixel circuit, drive circuit therefor, a display panel, and a display panel
A technology of pixel circuit and driving method, which is applied in the field of display, can solve problems such as afterimages of display panels, and achieve the effect of solving the problem of afterimages
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example 1
[0108] by Figure 4 Take the pixel circuit shown as an example, an input and output timing corresponding to the pixel circuit is as follows Figure 10a shown. Specifically, select Figure 10a The three stages P1, P2 and P3 in the input timing diagram are shown.
[0109] In the phase P1 (that is, the first reset phase), Scan1=0, Scan2=1, Scan3=0, Emit1=0, Emit2=1. The first switching transistor T1 is turned on to reset the gate of the driving transistor DT, and the potential of the first node N1 is Vint1. The fourth switching transistor T4 is turned on to reset the first pole of the driving transistor DT, and the potential of the second node N2 is VDD. The sixth switch transistor T6 is turned on to reset the anode of the light emitting diode oled, and the potential of the third node N3 is Vint2. The second switch transistor T2, the third switch transistor T3 and the fifth switch transistor T5 are turned off, and the light emitting diode oled does not emit light.
[0110] ...
example 2
[0116] Specifically, due to the signal delay, in order to avoid writing the data signal to the second node N2 before the fourth switching transistor T4 is turned off, the first reset phase and the data writing phase may also include a second reset phase, Figure 4 An input and output timing corresponding to the pixel circuit shown is as follows Figure 10b shown. Specifically, select Figure 10a The four stages P1, P1', P2 and P3 in the input timing diagram shown.
[0117] The working process of the P1, P2 and P3 phases is the same as that of the P1, P2 and P3 phases in Example 1, and will not be repeated here. The P1' stage, that is, the second reset stage, will be described in detail below.
[0118] In the phase P1' (that is, the second reset phase), Scan1=0, Scan2=1, Scan3=0, Emit1=1, Emit2=1. The first switching transistor T1 is turned on to reset the gate of the driving transistor DT, and the potential of the first node N1 is Vint1. The sixth switch transistor T6 is ...
example 3
[0120] Specifically, in order to reduce signal terminals, the third scanning signal terminal and the first scanning signal terminal may be the same signal terminal. by Figure 5 Take the pixel circuit shown as an example, an input and output timing corresponding to the pixel circuit is as follows Figure 10c shown. Specifically, select Figure 10c The four stages P1, P1', P2 and P3 in the input timing diagram shown.
[0121] Specifically, compared with the second example, except the sixth switching transistor T6, the working states of other transistors are the same as those of the second example. In the second example, the sixth switch transistor T6 is turned on in the three stages of P1, P1' and P2, but in this example the sixth switch transistor T6 is turned on only in the stages of P1 and P1'.
[0122] Although the present example can reduce the number of signal terminals compared with the example 2, the example 2 can make the reset potential of the third node N3 last u...
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