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Adaptive Wear Leveling

A technique for corresponding blocks, marks, applied in the direction of instrumentation, input/output to record carriers, calculations, etc.

Active Publication Date: 2020-06-23
WESTERN DIGITAL TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In practice, however, physical blocks do not all have the same durability
Thus, a flash memory system may reach its specific end of life, while many physical blocks are still available at this point

Method used

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Embodiment Construction

[0015] The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configurations in which the subject technology may be practiced. The accompanying drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the subject technology. However, the subject technology is not limited to the specific details set forth herein and can be practiced with one or more implementations. In one or more instances, structures and components are shown in block diagram form in order to avoid obscuring concepts of the subject technology.

[0016] In the subject system for adaptive wear leveling, prior to utilizing the flash memory circuits of the flash memory system for data storage, the flash memory circuits on each flash memory circuit (e.g., a single flash memo...

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Abstract

A device that provides adaptive loss leveling includes at least one processor. At least one processor performs data storage operations using block groups of flash memory circuits, each block group including blocks from each flash memory circuit and at least some blocks marked active for data storage operations. When a block marked as active is used for data storage operations, at least one processor monitors the quality metric of each block. At least one processor determines when a block's quality metric is below a minimum level and marks the block as temporarily inactive, wherein when marked as temporarily inactive, the block is not used for data storage operations. When the criteria are met, at least one processor marks the block as active so that the block can be used again for data storage operations.

Description

[0001] Cross References to Related Applications [0002] This application claims priority to US Provisional Patent Application Serial No. 62 / 368,967, filed July 29, 2016, entitled "Adaptive Wear Leveling," the entire contents of which are hereby incorporated by reference for all purposes. technical field [0003] The present description relates generally to wear leveling, including adaptive wear leveling, for flash memory devices. Background technique [0004] In flash memory systems, to achieve high endurance, the system typically employs a wear leveling algorithm that keeps all physical blocks within a tight cumulative program / erase (P / E) cycle range. It is assumed that the physical blocks all have the same durability (when ignoring weak blocks that are compensated for due to overprovisioning), and thus will all wear out substantially at the same time. In practice, however, physical blocks do not all have the same durability. Thus, a flash memory system may reach its spe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
CPCG06F3/0616G06F3/0634G06F3/064G06F3/0653G06F3/0679G06F12/0246G06F2212/1036G06F2212/7211G06F3/0629G06F3/0649G06F3/0659G06F3/0647
Inventor R.D.巴恩特A.G.科梅蒂S.T.凯泽
Owner WESTERN DIGITAL TECH INC