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Memory cell states in valleys between adjacent data states

A memory unit and data state technology, applied in static memory, digital memory information, read-only memory, etc., can solve problems such as degradation of distinguishing ability and difficulty in sensing operation

Active Publication Date: 2021-05-07
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, MLCs can present difficulties with sensing operations because the ability to distinguish between adjacent data states can degrade over time and / or operation

Method used

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  • Memory cell states in valleys between adjacent data states
  • Memory cell states in valleys between adjacent data states
  • Memory cell states in valleys between adjacent data states

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Embodiment Construction

[0016] Memory devices may include error correction circuitry (eg, implementing error correction code (ECC)) to correct for errors in sensing the data state of memory cells. Some kind of error correction circuitry can operate more efficiently with soft data. Hard data is data that corresponds only to the data state of a memory cell. For example, a 2-bit memory cell can be programmed to one of four data states, where each data state corresponds to one of the hard data 00, 01, 10, or 11. In contrast, soft data associated with a memory cell may indicate a position within a distribution of states (eg, a Vt distribution) of a state (eg, a threshold voltage (Vt)) representative of a target state to which the memory cell is programmed. Additionally, soft data associated with a memory cell may indicate a probability of whether the state of the memory cell corresponds to the target state to which the memory cell was programmed. However, transmitting soft data along with hard data may ...

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Abstract

The present invention includes apparatus and methods related to memory cell states that are in valleys between adjacent data states. Several methods can include determining whether a state of a memory cell is in a valley between adjacent distributions of states associated with respective data states. The method may also include transmitting a signal indicative of a data state of the memory cell and whether the state of the memory cell is in the valley.

Description

[0001] Information about divisional applications [0002] This application is a PCT application with an international filing date of July 31, 2013, an international application number of PCT / US2013 / 052942, and an invention title of "Memory cell state in a valley between adjacent data states" entering the Chinese national phase A divisional application of the invention patent application with application number 201380047414.3. technical field [0003] The present disclosure relates generally to semiconductor memory and methods, and more particularly to apparatus and methods related to states of memory cells that are in valleys between adjacent data states. Background technique [0004] Memory devices are often provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error inform...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/52G11C16/04G11C16/06G11C16/26G11C16/34G11C11/56G06F11/10
CPCG06F11/1048G06F11/1068G06F11/1072G11C11/5642G11C16/0483G11C16/06G11C16/26G11C16/3418G11C29/52
Inventor 西瓦格纳纳穆·帕塔萨拉蒂帕特里克·R·哈亚特穆斯塔法·N·凯纳克罗伯特·B·艾森胡特
Owner MICRON TECH INC