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A Highly Compatible Programmable Neural Network Acceleration Array

A neural network and compatibility technology, applied in the direction of electrical program control, sequence/logic controller program control, etc., can solve problems such as poor performance, failure to meet performance requirements, and limit the development of deep learning intelligence

Active Publication Date: 2020-07-07
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Nowadays, the development of custom deep learning acceleration chips on mobile devices is becoming more and more popular. The challenge is that the performance of chips is limited by the type of deep learning network, such as CNN (convolutional neural network), RNN (recurrent neural network), in order to design high Energy-efficient custom deep learning accelerator chips, which are often optimized for certain networks, perform very well when using these networks, and perform poorly on other networks
However, due to the recent rapid development in the field of deep learning, an improved version of CNN or RNN network may appear in the future, and even other new deep learning neural network algorithms will appear, so the existing dedicated deep learning acceleration chips will not be able to achieve the desired results. The required performance requirements fundamentally limit the development of deep learning intelligence

Method used

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  • A Highly Compatible Programmable Neural Network Acceleration Array
  • A Highly Compatible Programmable Neural Network Acceleration Array
  • A Highly Compatible Programmable Neural Network Acceleration Array

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Embodiment Construction

[0015] The invention is described more fully hereinafter in reference to the examples illustrated in the illustrations, providing preferred embodiments but should not be considered limited to the embodiments set forth herein.

[0016] figure 1 Shown is a schematic diagram of the architecture of the highly compatible programmable neural network acceleration array of the present invention, wherein the central controller 11 is responsible for the global control of the deep learning neural network, and the feature vector transmitter 12 is responsible for transmitting the required information to all neural network computing unit chips 13. Feature vector.

[0017] The neural network computing unit slice of the present invention includes all basic deep learning algorithm computing modules, such as figure 2 As shown, the computing unit chip includes a programmable multiplication and addition unit 21 , a programmable activation unit 22 , an on-chip controller 23 , and a buffer 24 . ...

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Abstract

The invention belongs to the technical field of integrated circuits, specifically a high-compatibility programmable neural network acceleration array. The array employs a reconfigurable architecture,and comprises one central controller, one feature vector transmitter, and a plurality of neural network calculation unit pieces. The neural network calculation unit pieces comprise a programmable multiplication and addition unit, a programmable activation unit and a unit piece controller, and the acceleration array carries out the communication between any unit pieces through a programmable communication route. The acceleration array can be compatible with various types of neural network algorithms, does not lose the high energy efficiency, and is suitable for various types of deep learning intelligent systems.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a highly compatible programmable neural network acceleration array. Background technique [0002] Nowadays, the development of custom deep learning acceleration chips on mobile devices is becoming more and more popular. The challenge is that the performance of chips is limited by the type of deep learning network, such as CNN (convolutional neural network), RNN (recurrent neural network), in order to design high Energy-efficient custom deep learning accelerator chips are often optimized for certain networks, with high performance when using these networks, and poor performance under other networks. However, due to the recent rapid development in the field of deep learning, an improved version of CNN or RNN network may appear in the future, and even other new deep learning neural network algorithms will appear, so the existing dedicated deep learning accele...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G05B19/04
CPCG05B19/04
Inventor 陈迟晓史传进张怡云
Owner FUDAN UNIV