Test system for DSP (digital signal processing) unit in field programmable gate array chip

Abstract

The invention relates to a test system for a DSP (digital signal processing) unit in a field programmable gate array chip. The system includes a clock manager, a first memory, a DSP unit to be tested,a second memory, a third memory, and a test unit; a clock frequency at which data are written into the second memory is the same as the operating frequency of the first memory and the DSP unit to betested; a clock frequency at which data are read from the second memory is the same as the operating frequency of the third memory and the test unit; the clock manager is suitable for providing a first clock frequency and a second clock frequency, wherein the first clock frequency is greater than the second clock frequency; and the DSP unit to be tested is suitable for acquiring excitation data from the first memory at the first clock frequency, performing predetermined arithmetic operation on the excitation data and outputting operation result data to the second memory. With the above systemadopted, the accuracy of the test of the function of the DSP unit under a high frequency can be improved.

Description

technical field [0001] The invention relates to the technical field of testing, in particular to a testing system for a DSP unit in a field programmable gate array chip. Background technique [0002] Field Programmable Gate Array (Field-Programmable Gate Array, FPGA) is further developed on the basis of programmable devices such as Programmable Logic Array (Programmable Logic Array, PAL) and General Logic Array (Generic Logic Array, GAL). of. As a semi-custom circuit in the field of application-specific integrated circuits (ASIC), FPGA not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gate circuits. [0003] In recent years, FPGA chips have been widely used in various fields. With the increase of the size and complexity of the FPGA chip, in the design stage, the function verification of each logic unit becomes the key to FPGA chip design. [0004] As a basic logic unit in the FPGA...

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Problems solved by technology

[0005] However, the above-mentioned test method usually tests the function of the DSP unit when the DSP clock frequency is low. When the function of the DSP unit is tested under the condition of a high DSP clock frequency, the DSP unit may function normally, but the test results show that the function Unusual situation, less accurate

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