113 results about "Field programmable gate array chip" patented technology

The invention provides a field programmable gate array chip layout method. The method includes providing structural information of a logic unit of a field programmable gate array chip and net list information, generated after packaging, of a logic module; establishing a wiring resource map according to the structural information of the logic unit of the chip; arranging the field programmable gate array chip according to the net list information and the wiring resource map, and quickly wiring simultaneously. By the method, quick wiring is realized in the overall arrangement process according to the wiring resource map, and overall arrangement and wiring are closely combined, so that wiring success rate is increased, time delay of a circuit is reduced, and wiring resource utilization rate is increased.

The invention discloses a temperature compensation system and a temperature compensation method for a capacitance type micro-mechanical accelerometer. The temperature compensation system for the capacitance type micro-mechanical accelerometer comprises a capacitance type micro-mechanical acceleration sensor, a driving signal generating circuit, a capacitance / voltage switching circuit, an analog band-pass filter, a first digital / analog (D / A) converter, an analog / digital (A / D) converter, a second D / A converter, a third D / A converter and a field programmable gate array chip. The temperature compensation method for the capacitance type micro-mechanical accelerometer comprises three steps of: carrier wave generating / synchronously demodulating, resonance frequency locking and zero offset temperature compensating. According to the invention, the temperature change of a capacitance type micro-mechanical acceleration sensor is detected by the means that the resonance frequency of the capacitance type micro-mechanical acceleration sensor changes along with the change of the temperature, and the temperature compensation system is used for compensating the temperature by the means that the resonance frequency is taken as a compensation reference signal of an output signal of a capacitance type micro-mechanical accelerometer system. Therefore, the temperature compensation cost is reduced, the influence of temperature measurement errors on compensation precision is eliminated, and the temperature compensation precision is improved.

The invention discloses a resonant fibre-optic gyro signal detection method and device based on the coordinate rotary digital computer algorithm. The detection method includes the modulation signal production and the signal demodulation method, which are all reached by the phase bit / scope switch module based on the coordinate rotary digital computer algorithm. The detection device includes the laser, the coupler, the phase bit modulator, the fibre-optic ringer, the photoelectrical detector, the present programme array chip, the digital / module switcher, the sample collecting channel, the reactive circuit and the signal output channel. The invention can reach the two circuits of the modulation signal production, demodulation and treatment by using the coordinate rotary digital computer algorithm; the scope, phase bit and frequency is dispatched by the programme, which is benefit for the detection system stable and assembly; the algorithm is determined by the iterative times and data word length; the fibre-optic ringer can avoid the light wave in fibre-optic back to the laser and influence the laser stable.

The invention discloses a testing apparatus for fixed series compensation protection. A current transformer is used for converting a current analog quantity into a small voltage signal. A low-pass filtering module is use for filtering the small voltage signal. An analog-digital conversion module is used for sampling and maintaining an analog quantity input by the low-pass filtering module, and sending an obtained digital quantity to a signal processing module. The signal processing module is used for conducting caching, data zooming and communication protocol transformation, and enables data to be packed and written in a field programmable gate array chip. The field programmable gate array chip is used for driving a photoelectric conversion module to convert the data into an optical signal that supports a preset communication protocol, and sends the optical signal to a to-be-tested protection apparatus through a fiber interface. The invention also discloses a testing method for fixed series compensation protection. According to the invention, the protection function of a series compensation protection apparatus can be checked in a quantified manner, and the testing apparatus and method are suitable for debugging an intelligent transformer substation.

The invention belongs to the technical field of satellite navigation and relates to a programmable navigational satellite spread spectrum sequence generator. The programmable navigational satellite spread spectrum sequence generator comprises input / output modules, a configurable logic unit, a digital clock management module and a block memory which are integrated into a field programmable gate array chip. The programmable navigational satellite spread spectrum sequence generator is characterized in that: different pseudorandom sequence generating methods for different navigation systems by using the spread spectrum sequence generator can be implemented by connecting 1 to 6 code generator units in series or in parallel; and all the code generator units are provided with identical working condition controllers, state shifting controllers, feedback controllers, initial registers and output controllers. The programmable navigational satellite spread spectrum sequence generator is used forgenerating pseudorandom codes in a satellite signal simulator, so the programmable navigational satellite spread spectrum sequence generator has the advantages of greatly reducing expenditure of hardware resources, reserving a larger space for perfecting other functions, and greatly reducing workload of the conventional real-time generating mode, along with easy maintenance.

The invention discloses a current measurement device for a high-voltage converter, which is connected with a high-voltage circuit, and the high-voltage circuit supplies input power supply for the device. The device comprises a current sensor, an A / D converter, a field programmable gate array chip, a fiber driver and an isolation voltage stabilizing power supply, wherein the current sensor is connected with a circuit end of the high-voltage circuit, and is connected with the A / D converter; the A / D converter is connected with the field programmable gate array chip; the field programmable gate array chip is connected with the fiber driver; the fiber driver is connected with the isolation voltage stabilizing power supply; and the isolation voltage stabilizing power supply is connected with the high voltage circuit. The device overcomes the defect of the prior art to solve the problem of quick measurement of current of the high-voltage converter.

The invention relates to the technical field of chip interconnection, in particular to an FPGA-based interconnection device among chips. According to the FPGA-based interconnection device among the chips, a dynamic clock adjusting module, a low-voltage differential signal sending module and a low-voltage differential signal receiving module are arranged in each FPGA chip so that information transmission between the FPGA chips can be achieved. The interconnection device has the advantages of being adjustable in speed and high in flexibility.

This invention provides a method and device for video-stream frame rate adaptation. The method includes: allocating a buffer space for each of at least one video conference room respectively and dividing the buffer space into at least one segment, each segment of which is used for buffering a video frame; and performing following steps for each of the at least one video conference room: generating a pulse signal for the video conference room periodically according to a certain pulse rate; and performing a data writing operation for a segment of the corresponding buffer space at an input-video-stream frame rate of the video conference room, and performing a reading operation for a segment of the buffer space at an output-video-stream frame rate. This invention also provides an FPGA chip and a video stream processing apparatus. The invention simplifies frame rate adaptation design, and reduces system processing overhead during the frame rate adaptation.

This invention discloses a 155M error analysis tester based on a site programmable gate array composed of a tested device, a clock data extraction and recover chip, a clock synthetic chip, a site programmable gate array chip, a single-chip processor, a liquid crystal display screen, a bit error pilot lamp, a film key board and a serial communication interface. The site programmable gate array includes a count module.