14 results about "Field programmable gate array chip" patented technology

The application belongs to the technical field of wind turbine simulation, and provides a wind turbine full-closed loop simulator and method based on a field programmable gate array, which comprises a field programmable gate array chip, an ARM chip and a digital-analog interface connected with the field programmable gate array chip; the application adopts the field programmable gate array chip, and realizes transient real-time simulation of the electromagnetic system of the wind turbine by means of the powerful parallel computing capability of the field programmable gate array chip; compared with the prior art, the application can quickly verify the effect of the control strategy by using the built-in controller, and can access the actual wind turbine controller through the digital-analog interface to perform hardware-in-the-loop simulation and test the control effect; meanwhile, the ARM chip is used as a real-time operation carrier of the wind turbine controller algorithm, and the field programmable gate array chip and the ARM chip interact with real-time data through a digital-analog channel to realize a wind turbine closed loop real-time simulation platform.

The utility model relates to the technical field of target detection, in particular to a target detection circuit and a field programmable gate array chip. The circuit comprises a cache module and a detection module, wherein the detection module comprises a first detection unit, a second detection unit and an output unit; the first detection unit outputs a first detection result to the output unit according to Doppler dimension data; the second detection unit outputs a second detection result to the output unit by detecting distance dimension data input by the cache module; and the output unit outputs a target detection result according to the first detection result and the second detection result. In this way, Doppler dimension detection is completed while data are cached once, and distance dimension detection is completed when cached data are read, so that resource consumption is reduced, and delay of read-write operation is reduced.

The invention provides a chip program burning adapter and a chip program burning method and system, and relates to the technical field of chip program burning. The chip program burning adapter comprises a universal burning base, a field programmable gate array (FPGA) chip and a flash memory chip; a plurality of slots are formed in the universal burning base, and the universal burning base is in plug-in connection with pins of at least one chip to be burnt through the slots; a plurality of slots of the universal burning base are respectively connected with corresponding interfaces on the FPGA chip; the FPGA chip comprises an online programming interface, a storage interface and a program burning interface, the online programming interface is used for being connected with an upper computer, the storage interface is used for being connected with the flash memory chip, and the program burning interface is used for being connected with a burner. The adapter disclosed by the invention has relatively high universality, and different chips to be burnt can be adapted without designing one adapter for each chip.

A server system and a communication method of a server system are provided. The server system includes: at least one first processor board and a host server; the first processor board includes a first field programmable gate array chip and a first processor chip, the first field programmable gate array chip and the first processor chip being packaged and interconnected; the host server is configured to transmit host data to the first field programmable gate array chip through the switching network; and the first field programmable gate array chip is configured to process the host data, receive request data sent by the first processor chip, generate a communication protocol message according to processed host data and the request data, and transmit the communication protocol message to a target processor board through the switching network.

The invention provides a video transmission device and method, the video transmission device comprises a protection shell, at least two camera modules, a video processing assembly and a power supply, and the protection shell comprises an accommodating cavity; the at least two camera modules are arranged in the containing cavity, the at least two camera modules are arranged in the first direction in an angular interval mode, and the at least two camera modules are used for collecting imaging conditions in different directions in the external environment; the video processing assembly is arranged in the accommodating cavity, the video processing assembly comprises a field programmable gate array (FPGA) chip, an optical fiber transceiver and at least two connectors, and the at least two camera modules are respectively in communication connection with the corresponding connectors through flat cables; the input end of the FPGA chip is in communication connection with the connector, and the output end of the FPGA chip is in communication connection with the optical fiber transceiver; and the power supply is arranged in the accommodating cavity and is used for supplying power to the camera module and the video processing assembly. The cost of the video transmission device can be reduced.

This application discloses an in-vehicle domain controller, electrical equipment, data communication method, and computer-readable storage medium. The in-vehicle domain controller includes a field-programmable gate array (FPGA), a first system-on-a-chip (SoC), and at least one second SoC, each SoC being electrically connected to the FPGA. The first SoC is configured to establish a first high-speed serial computer expansion bus standard link with the FPGA. The second SoC is configured to establish a second high-speed serial computer expansion bus standard link with the FPGA if the first high-speed serial computer expansion bus standard link fails to be established. Thus, by switching to the second high-speed serial computer expansion bus standard link in the event of a failure in establishing the first high-speed serial computer expansion bus standard link, uninterrupted data transmission and stable operation of vehicle functions can be ensured.

The application relates to the technical field of communication, in particular to a distributed base station system, which comprises at least: a plurality of baseband chips, the baseband chips being UCP4008 chips; a field programmable gate array chip, a first data end of the field programmable gate array chip being connected with the plurality of baseband chips through optical fibers and performing data interaction with the baseband chips through a JESD protocol; a first data end and a second data end of a network switching device being communicatively connected with the plurality of baseband chips, the network switching device being used for realizing data interaction between a core network and the baseband chips; and a front panel device, a first data end of the front panel device being communicatively connected with a second data end of the field programmable gate array chip, the front panel device being used for transmitting data sent by the field programmable gate array chip to an air interface through a radio frequency antenna to provide a mobile access service function. The distributed base station system is lower in cost under the premise of guaranteeing overall performance.

The invention relates to the technical field of signal processing, and provides a local reconfigurable digital signal processing method, device and equipment and a medium, the local reconfigurable digital signal processing method comprises the steps of analyzing a function switching instruction to obtain a target switching function and configuration parameters, performing resource evaluation based on the target switching function, and obtaining a local reconfigurable digital signal. And obtaining a corresponding resource evaluation result according to the target switching function, the configuration parameter and the resource evaluation result, determining reconstruction data according to the target switching function, the configuration parameter and the resource evaluation result, performing function reconstruction on the field-programmable gate array chip based on the reconstruction data, and further performing digital signal processing based on the field-programmable gate array chip after function reconstruction. Switching of multiple functions is achieved on one field programmable gate array, the resource utilization efficiency is improved, the function switching flexibility is enhanced, the requirements for functional diversity and real-time performance under different application scenes are met, and meanwhile the hardware cost and complexity are reduced.

Embodiments of the present application provide a phase shift code calculation method based on a field programmable gate array chip and an electronic device. The field programmable gate array chip includes a plurality of exchange units. The plurality of exchange units perform the following method in parallel. For one exchange unit, in response to ultra-wideband positioning information input for a receiving antenna, trigonometric function data is calculated. A plurality of time sequence operations are performed between the trigonometric function data and a preset parameter to obtain an intermediate variable. The intermediate variable and a longitudinal coordinate power corresponding to the receiving antenna are input into a multiplier of the field programmable gate array chip to obtain a data result output by the multiplier. The data result is processed using a plurality of interval segments and a limited phase shift accuracy to obtain a phase shift code of the receiving antenna. Based on the above method, the calculation process of the phase shift code is processed in parallel, the storage occupation of data is reduced, the algorithm power consumption is reduced, and the overall calculation efficiency is improved.

The invention discloses a field programmable gate array chip, a light source modulation system and a light source modulation method based on an FPGA, and the chip comprises a signal collection module which is used for collecting a driving signal and an electric signal; the driving signal is generated by a signal generator; the electric signal is obtained by converting a collected optical signal by the photoelectric detector; the frequency sweep detection module is used for determining whether to enter a frequency sweep state or not according to a comparison result between the frequency change trend of the driving signal and a change threshold value; the signal modulation module is used for modulating the electric signal in a frequency sweeping state to generate a modulated electric signal; the signal optimization module is used for determining whether iterative optimization is carried out on the modulated electric signal or not according to a comparison result between the modulated electric signal and an ideal Gaussian waveform and a preset value, and determining an optimized electric signal; and the signal output module is used for transmitting the optimized electric signal to a driver of the light source. Therefore, the real-time performance and the flexibility of electric signal modulation are improved.

The invention relates to an embedded software automatic testing system and method based on hardware-in-the-loop, and relates to the technical field of embedded software automatic testing, and the embedded software automatic testing system comprises a hardware-in-the-loop platform and a software testing platform; the hardware-in-the-loop platform comprises a field programmable gate array (FPGA) chip, and the function of a pin can be changed by switching code streams; the verification period of a complex system is shortened and the defect detection rate is improved through the physical-level precision of hardware-in-the-loop and the intelligent arrangement capability of a software platform; user responsibilities are clearly divided, the standardization of the test process is ensured, and the misoperation risk is reduced; the whole process from test case writing to report generation is automatic, and manual intervention is reduced; multi-task parallel queuing and priority adjustment are supported, and the utilization rate of test resources is improved; the method is compatible with various hardware protocols, adapts to different types of target test boards, and enhances the system versatility.

The present disclosure provides a system and a method for vehicle sensor time synchronization, and a field programmable gate array chip, in the field of artificial intelligence, such as sensor, artificial intelligence chip, and autonomous driving. The system for vehicle sensor time synchronization includes: target vehicle sensors and a field programmable gate array chip, the target vehicle sensors include all vehicle sensors in a target vehicle that require a timestamp information to be written; the target vehicle sensors are connected to the field programmable gate array chip, and are configured to send collected sensor data to the field programmable gate array chip; the field programmable gate array chip is configured to write the timestamp information into the sensor data based on a system time of the field programmable gate array chip; wherein the field programmable gate array chip comprises: a system module and a logic module; the system module and the logic module are respectively connected to at least one of the target vehicle sensors based on a principle of load balancing, and are respectively configured to write the timestamp information into obtained sensor data based on the system time.

The application discloses a control circuit board, an electronic device and a control method of the circuit board. The control circuit board comprises a relay, a field programmable gate array (FPGA) chip and a lock control circuit. The relay is connected to a relay power supply through a switch circuit. The FPGA chip is connected to a working power supply and the relay. The lock control circuit is connected to the working power supply, the switch circuit and the FPGA chip. In response to abnormal working of the working power supply or the FPGA chip, the lock control circuit controls the switch circuit to be disconnected, so that the relay is in a locked state. According to the scheme, the relay lock control is realized through joint control of multiple signals, such as a working power supply abnormal signal and an FPGA chip abnormal signal, the relay misoperation is effectively prevented, and the reliability of the circuit is improved. The relay lock is realized by cutting off the power supply circuit of the relay power supply to the relay, the problem of unstable lock caused by internal faults or external interference of the relay is avoided, and the stability of the circuit is improved.

The invention relates to a password card data processing method and device, computer equipment, a storage medium and a computer program product. The method comprises the following steps: establishing high-speed serial computer expansion bus standard link connection with a field-programmable gate array chip, configuring a base address register of the field-programmable gate array chip, initializing a direct memory access engine of the field-programmable gate array chip, carrying out initialization setting on a scheduling acceleration module of an anti-quantum algorithm system on the field programmable gate array chip; constructing a descriptor table, wherein the descriptor table is configured to cooperate with the scheduling acceleration module to execute the operation of the anti-quantum algorithm system; the descriptor table is analyzed through the scheduling acceleration module, the anti-quantum algorithm system is called to execute calculation, and a calculation result is output to a target address. By adopting the method, the security and flexibility of the password card can be improved, and a traditional algorithm and an anti-quantum algorithm are compatibly supported.