FPGA-based interconnection device among chips

An inter-chip and chip-to-chip technology, applied in the field of FPGA-based inter-chip interconnection devices, can solve problems such as not involving LVDS interfaces, and achieve the effect of adjustable rate and high flexibility

Active Publication Date: 2014-09-10
SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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Problems solved by technology

[0003] There are many available technologies for the interconnection between chips. The LVDS (Low-Voltage Differential Signaling) interface has the characteristics of low noise, low power consumption, high speed, and low cost. When the speed requirement is not too high (usually These chips do not integrate serdes (serializer), and are often used as the interconnection interface between chips. In the existing technology, there is generally no LVDS interface with reliable data transmission and adjustable transmission rate.

Method used

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  • FPGA-based interconnection device among chips

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Embodiment 1

[0028] as attached figure 1 As shown, an FPGA-based inter-chip interconnection device is provided with a clock dynamic adjustment module, an LVDS sending module, and an LVDS receiving module in the FPGA chip.

[0029] Clock dynamic adjustment module:

[0030] In order to realize the dynamic reconfiguration of the rate, a dynamic reconfigurable clock scheme is adopted, and the reconfigured clock parameters are sent to the clock dynamic adjustment module in the FPGA in real time through the spi or iic interface connected to the CPU and the FPGA externally. The clock output by the adjustment module is the clock of the whole device.

[0031] LVDS sending module:

[0032] The peer chip will send a signal that the data is ready. When the peer module is ready to receive data, the fifo will read the data in the fifo every data bit width cycle. The read data will pass through the framing module, according to the header , data length, valid data, and data checksum and protocol format...

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Abstract

The invention relates to the technical field of chip interconnection, in particular to an FPGA-based interconnection device among chips. According to the FPGA-based interconnection device among the chips, a dynamic clock adjusting module, a low-voltage differential signal sending module and a low-voltage differential signal receiving module are arranged in each FPGA chip so that information transmission between the FPGA chips can be achieved. The interconnection device has the advantages of being adjustable in speed and high in flexibility.

Description

technical field [0001] The invention relates to the technical field of chip interconnection, in particular to an FPGA-based inter-chip interconnection device. Background technique [0002] FPGA (Field Programmable Gate Array) chip is a programmable logic device with short development cycle and high reliability. [0003] There are many available technologies for the interconnection between chips. The LVDS (Low-Voltage Differential Signaling) interface has the characteristics of low noise, low power consumption, high speed, and low cost. When the speed requirement is not too high (usually These chips do not integrate serdes (serializers), and are often used as interconnection interfaces between chips. In the existing technology, there is generally no LVDS interface that transmits data reliably and has an adjustable transmission rate. Contents of the invention [0004] In order to solve the problems in the prior art, the present invention provides an FPGA-based interconnecti...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
Inventor 秦刚刘强孙大军李长志
Owner SHANDONG CHAOYUE DATA CONTROL ELECTRONICS CO LTD
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