220 results about "Local circuit" patented technology

A system for controlling electricity consumption of an electricity consumer having a plurality of loads, including: (a) a main central processing unit, connected to a power source, and adapted to receive a signal therefrom; (b) a memory associated with the processing unit; (c) controlled relay assemblies connected to a plurality of loads via local circuit breakers, each assembly including: (i) a relay, responsive to the processing unit; (ii) a current sensor, electrically connected to the relay, the relay and the current sensor being electrically associated with the processing unit, and (iii) an electrical line having a first end connecting the relay assembly to the power source, and having a second end connecting to a local circuit breaker connected to at least one load; wherein each current sensor is adapted to provide, to the processing unit, data pertaining to current drawn via a particular local circuit breaker, and wherein the processing unit is configured to command the relay based on the signal received from the power source, and based on a set of rules provided to the processing unit, the set of rules including load priority information, such that each relay opens or closes in response to the command from the processing unit, so as to shut off or restore power to the electrical line.

A system and method for accurately distributing a master reference voltage to a plurality of local circuits within a system. A central master reference voltage is distributed to a plurality of local circuits as a difference in the voltage of a pair of conductors oriented substantially spatially parallel. Local reference voltages are generated based on the master reference voltage and a local voltage source.

One embodiment disclosed relates to a system for power management of a group of computers. The system includes server side infrastructure (SSI) circuitry at each computer in the group and a centralized power management module (CPMM). The SSI circuitry includes local monitoring circuitry coupled to a central processing unit (CPU) of the computer. The CPMM has a management link to the SSI circuitry at each computer in the group. The local circuitry at each computer monitors power consumption at the CPU of that computer and transmits power consumption data to the CPMM. The CPMM applies a set of rules to the power consumption data to determine when and at which computers to enable and disable a CPU power throttling mode.

A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms / cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.

An interlocked pipelined CMOS (IPCMOS) family of logic circuits provides extremely high performance pipelined operation and guarantees error free operation where variations in timing are compensated for automatically by the circuits. The IPCMOS logic circuits also provide a standard interface that makes it possible to interface different macro types easily. The IPCMOS logic circuits feature interlocking in both the forward and reverse directions. This "handshaking" guarantees error free timing and makes it possible to eliminate the need for a global clock at the macro level. Timing signals are generated locally at the macro level from the handshaking signals between macros. This makes it possible for the local circuits to deal with global timing variations caused by power supply noise, ACLV, and parameter variations. The macros operate in a pipelined mode with data advancing automatically from macro to macro with the timing controlled by the local handshaking signals. This pipelined operation results in an extremely fast cycle time. Another feature of IPCMOS is that the data inputs to a macro are only sampled when the data is in a valid state. making the concept of a standard macro interface possible. With this standard interface, different logic types such as static and dynamic circuits can be easily interconnected and the concept of reusable macros becomes a reality.

The invention discloses a double-phase-locked loop circuit and a control method thereof. The double-phase-locked loop circuit comprises a phase / frequency detector, a charge pump, a frequency adjustment circuit and an N frequency divider. The frequency adjustment circuit comprises a coarse adjustment circuit, a fine adjustment circuit and a current-controlled oscillator, wherein the coarse adjustment circuit is used for coarse adjustment of frequency of output signals of phase-locked loops till approaching a target frequency; the fine adjustment circuit is used for fine adjustment of the frequency of the output signals of the phase-locked loops till the target frequency; and the current-controlled oscillator is coupled with the coarse adjustment circuit and the fine adjustment circuit and used for producing the output signals of the phase-locked loops, wherein the frequency of the output signals is the target frequency. The double-phase-locked loop circuit can effectively achieve the purpose of expanding the frequency adjustment range under the situation of keeping the loop bandwidth of the phase-locked loops smaller, realize the on-chip integration and further reduce the cost and the design complexity of the circuit.

A system and method for controlling the power consumption of an electronic display. A maximum current value may be selected where above this value the risk to damage to the display or local circuitry may be jeopardized. Ramp-wise and / or gradual controls of the display parameters such as fan speed and backlight levels may reduce the current draw during extreme situations and line voltage fluctuations. Embodiments allow the display to continue operation without risking an overload of the local circuit or damage to the display. Further embodiments may be used to limit the power consumption of a display in order to minimize energy usage. Several parameters can be measured and controlled simultaneously to provide a minimal amount of energy usage while minimizing any noticeable difference in images.

The invention discloses a signal conditioning circuit, a conditioning method thereof and a double sampling retaining circuit. The signal conditioning circuit comprises a first chopping switch, a programmable gain amplifier, a second chopping switch, a double sampling retaining circuit, an analog-to-digital converter, and a digital reduction sampling filter which are connected in sequence. The double sampling retaining circuit samples outputs of the programmable gain amplifier in two-phase positions of a chopping clock, and the results of two samplings are added. and an added output voltage is transmitted to and processed by the analog-to-digital converter, and the digital reduction sampling filter. Since the double sampling retaining circuit is added, the invention avoids the residual and off-tune problem in a chopping amplifier. Meanwhile, the invention facilitates the integration of a single chip, without the need of external filtering capacitor. Furthermore, a novel sequential control reduces the consumption of a digital signal conditioning circuit based on a chopping amplifier.

A system and method for controlling the power consumption of an electronic display. A maximum current value may be selected where above this value the risk to damage to the display or local circuitry may be jeopardized. Ramp-wise and / or gradual controls of the display parameters such as fan speed and backlight levels may reduce the current draw during extreme situations and line voltage fluctuations. Embodiments allow the display to continue operation without risking an overload of the local circuit or damage to the display. Further embodiments may be used to limit the power consumption of a display in order to minimize energy usage. Several parameters can be measured and controlled simultaneously to provide a minimal amount of energy usage while minimizing any noticeable difference in images.

A dual eye motion detector assembly comprising a main infrared sensor head and a secondary infrared sensor head mounted on a mounting box. The main motion sensor head is pivotally mounted to the mounting box and contains a standard infrared motion sensor with an approximate 90 to 180 degree viewing zone. The secondary motion sensor head is also pivotally and independently mounted to the mounting box and contains its own standard infrared motion sensor with an approximately 90 to 180 degree viewing zone. The two motion sensors in the main and secondary motion sensors heads are connected to a circuit panel located the main sensor head. Control switches are mounted on the sides of the main infrared sensor head to control sensitivity and timing. Outside electrical current is delivered to the circuit panel and divided into local circuits to control the operation of at least one lamp so that when an infrared-emitting object passes into the viewing zone of either sensor head, the lamp is automatically activated.

An automatically switchable dual-power-circuit-loop circuit system selectively supplies a first power source through a first voltage output circuit loop to an output terminal, and a second power source is selectively supplied through a second voltage output circuit loop to the output terminal. A switching control circuit functions to detect the first output voltage of the first voltage output circuit loop. When the first output voltage regularly supplies electrical power, the first power source is supplied through the first voltage output circuit loop to the output terminal, while the switching control circuit generates a switching signal to switch a switching element to an open-circuit condition thereby cutting off the second voltage output circuit loop. When the first power source fails to supply power, the switching element is set in a closed-circuit condition to allow the second power source to be supplied through the second voltage output circuit loop to the output terminal.

This invention relates to a liquid measure device which comprises measure electrode, display circuit, measure and control electrode and power circuit. The measure electrodes are more than two, which comprises liquid electrode and a loop circuit on the liquid bottom. And the measure and control circuit comprises pulse generator circuit, process circuit composed of semi-conductor switches and couple circuit connected with each liquid level electrode. The couple circuit has three ends and each of them is separately connected with the output end of the pulse generator circuit, input end of process circuit and liquid level electrode. The loop circuit electrode is connected with earth line of the power. The pulse generator circuit sends out pulse electricity wave with certain dutycycle to the liquid level electrode through couple circuit. The process circuit processes the electricity level of the liquid level electrode through relevant couple circuit and sends out the liquid level signals to the display circuit or outer circuit.

This invention includes an electronic device that has both electrical contacts for coupling to local, application specific circuitry and contacts for supplying power to another electronic device. The electronic devices may be coupled in series, so as to eliminate the need for bulky, unsightly cables or wires. Since the devices may be coupled in series ad infinitum, the possibility exists that the series combination of devices may draw more power than either a power source can provide or sensitive internal circuitry, like fuses for example, can handle. As such, each electronic device includes a current limiting circuit having a current sense circuit and a switch coupled serially between the input and the output that powers the next electronic device. When the current drawn from the input to the output supplying power for the downstream devices exceeds a predetermined threshold, the switch deactivates the upstream chargers local circuitry. Once the downstream devices have completed their desired activities, the current drawn by the downstream devices will be reduced. When this occurs, the current sense circuits of the upstream devices will detect that the total current drawn has fallen below the predetermined threshold and will once again reactivate their local circuitry. In one embodiment, the electronic devices are desktop battery chargers. By disabling upstream battery chargers while downstream battery chargers complete their charging cycle, the current limiting devices in the upstream battery chargers ensure that fuses disposed within the upstream battery chargers do not blow. A blown fuse in an upstream charger could result in the entire series combination losing power. By including the current limiting circuit of the invention, a user may couple as many series devices together as they want without fear of blowing fuses in the upstream devices.

An LED power supply device has a loop circuit formed by a switching circuit, an LED and a comparison circuit, and a reference voltage generation circuit for providing reference voltage to the comparison circuit. The loop circuit oscillates so that substantially constant current is applied to the LED.

A local circuit cooperates with a video camera and a trigger signal source such as an existing alarm trigger in an intruder alarm system. A trigger signal causes the local circuit to sample the video camera output and forward one or more images together with date and time information via a public communications channel to a data warehouse where the data is stored in raw, as-received form. The stored data is used to reconstitute one or more images only if necessary, for example if an actual intrusion has occurred.

One embodiment disclosed relates to a system for power management of a group of computers. The system includes server side infrastructure (SSI) circuitry at each computer in the group and a centralized power management module (CPMM). The SSI circuitry includes local monitoring circuitry coupled to a central processing unit (CPU) of the computer. The CPMM has a management link to the SSI circuitry at each computer in the group. The local circuitry at each computer monitors power consumption at the CPU of that computer and transmits power consumption data to the CPMM. The CPMM applies a set of rules to the power consumption data to determine when and at which computers to enable and disable a CPU power throttling mode.

The invention discloses a filament open circuit protector used in airport beacon light adjustment system with constant current. The protector is a four-end device composed of minitype electrical source, minitype relay, semiconductor double-way switch and voltage detecting circuit, which is connected in series between isolation transformer secondary socket and halogen lamp plug of airport beacon light adjustment system with constant current. When load circuit is normal, the protector doesn't affect normal working; once load opening circuit, the protector shorts isolation transformer secondary immediately, and makes isolation transformer in idle load working state, accordingly, possibility that can cause damage of isolation transformer secondary circuit opening circuit processing caused by airport beacon light adjustment system filament open circuit with constant current can be completely eradicated. Operation maintenance cost is reduced, labor intensity of staff is lightened, working efficiency is increased and operating reliability of beacon light system and safety of airplane rise-and-down are enhanced.

The invention provides a register time-out hour consultation method, a cancellation and a users separation method, a re-register method and a cancellation method, wherein, the register time-out hour consultation method comprises the following steps: S402, after the circuit domain position is updated successfully, the local circuit domain access adaptation function entity starts register or re-register requests to the IP multimedia subsystem on circuit domain conversation control paths, and users registers or re-registers request message carries updating times of the positions of circuit domain; S404, the calling conversation control function entity of the IP multimedia subsystem refreshes time according to the circuit domain and sets register time-out hours according to local strategies; and S406, the calling conversation control function entity sends response messages of registering that includes the register time-out hour or re-registering successfully to the local circuit domain access adaptation function entity.

A contactless IC card having an antenna, a transmit / receive circuit for recovering data (clock) and electric power from a carrier signal received by the antenna, a logic circuit operated with the electric power supplied thereto from the transmit / receive circuit, and a memory. The transmit / receive circuit has a rectifier circuit for outputting data (clock) and rectifier circuits for electric power in such a manner that the carrier signal is inputted to each of the rectifier circuit for outputting data (clock) and the rectifier circuit for electric power. With this configuration, high frequency matching can be optimized separately for the rectifier circuit for outputting data (clock) and the rectifier circuit for electric power. It is also possible to separately optimize adjustments to a voltage of recovered data (clock) and a recovered supply voltage.

The invention discloses an experimental system for simulating a single event effect (SEE) of pulse laser based on an optical fiber probe, aiming to reduce beam spot diameter of the pulse laser and realize simulation of the SEE at a single device or a local circuit in a deep sub-micron integrated circuit. The system is composed of a pulse laser, an optical fiber probe and a probe platform, and the aperture of the conical tip of the optical fiber probe is 10nm-1mu m; the input end of the optical fiber probe is connected with the pulse laser, the optical fiber of the optical fiber probe close to the output end is fixed in a probe clip of the probe platform, the output end of the optical fiber probe is contacted with the detected position of an integrated circuit chip, and the optical fiber probe transmits the pulse laser to the output end from the input end; and the integrated circuit chip adopts two modes of being arranged or not arranged in a single event effect detection circuit board. By the invention, pulse laser with the beam spot diameter no more than 1 mu m can be output, thus realizing simulation of the SEE at a single device or a local circuit in a deep sub-micron integrated circuit and lowering the cost.

A method and system for layout optimization relative to lithographic process windows which facilitates lithographic constraints to be non-localized in order to impart a capability of printing a given circuit with a process window beyond the process windows which are attainable with conventional simplified design rules. Pursuant to the method and system, lithographic capability and process windows are maximized to satisfy local circuit requirements and in order to achieve a maximally efficient layout. In this connection, there is employed a method utilizing a generalized lithographic process window as a measure when layout optimization is extended to a degree beyond that achieved by the simple fixed design rules which are applied to the design rules obtained is the advantage that a lithographic process window is determined purely through the calculation of image intensities and slopes, and as a result, the method can be quite rapid in application because it is possible to take advantage of known methods for rapid calculation of image intensity, and because there is obviated the need for geometrical shape processing during optimization.

The invention provides a mixed ASTN construction method, which effectively combines OCS and OBS two exchange modesby constructing network to form a ring topological structure OBS network and OCS network combination, making majority service to reach target node via one hop. The method satisfies communication need of network of most conditions. When network service changes in a small range, service Optical path can not bear will continue to transmit along ring topology in OBS exchange style. The inventive networking technology is more simple and effective, network performance worsening degree is small arising from network dynamic change, network operation is more stable and possesses relatively high communications capability; furthermore, network algorithm realization is less difficult and practical.

The invention provides a circuit board defect detection method and device, wherein the method comprises the steps of obtaining a shooting image of a circuit board, inputting the shooting image into atrained instance segmentation model, obtaining a target pixel unit output by the instance segmentation model, and enabling the target pixel unit to be a pixel unit presenting defects in the shooting image, wherein the instance segmentation model learns to obtain image characteristics of the local circuit board with the defect, and defect detection is carried out on the circuit board according to the area proportion of the target pixel unit in the shot image. As the instance segmentation model learns to obtain the image features of the local circuit board with the defects, the target pixel unitwith the defect can be accurately positioned in the shot image, further verification is carried out according to the area proportion of the target pixel unit in the shot image so as to finally determine whether the circuit board has the defect, and the defect detection precision and efficiency of the detected circuit board can be improved.

The invention relates to an on-chip self-triggering single event transient pulse width measurement method and system. The system comprises a combined logic circuit which includes a target circuit module, a gating circuit module, a single event transient pulse width measurement module and a time-delay unit time delay calibration module. The invention provides the on-chip self-triggering single event transient pulse width measurement method and system characterized in that the self-triggering signal generation circuit is simple in structure and no special delay design is required.

The present solution relates to providing a call service in a communication system, where in response to recognizing a predetermined event related to a user terminal (UEA), it is checked (203, 204) whether the user terminal (UEA) is a roaming user terminal (UEA) roaming in a visited packet switched network. It is also checked (203, 204) whether the user terminal (UEA) is defined to use a home network routing function in the visited packet switched network. If the user terminal (UEA) is a roaming user terminal (UEA) roaming in the visited packet switched network and defined to use the home network routing function in the visited packet switched network, the home network routing function is over overridden by performing (209) a forced setup of the call service to a local circuit switched network.

The present invention discloses a flat panel display (FPD), a light emitting module for use in the FPD, and an integrated circuit for use in the light emitting module. The light emitting module includes: at least one light emitting device string; and a local circuit for controlling current through the light emitting device string and generating a local feedback signal, wherein the local circuit has a first terminal for receiving power, a second terminal for coupling to the light emitting device string to control the current through the light emitting device string, a third terminal for generating the local feedback signal, and a fourth terminal for coupling to ground. The wiring of the FPD is therefore simplified.

The invention relates to a high-speed yaw scanning control device for testing quality of electron beam current. A complicated programmable logic device is respectively connected with a serial communication circuit and the like; the serial communication circuit is connected with an industrial control computer; two synchronous waveform generating circuits respectively comprise a digital to analog conversion circuit, a low-pass filter circuit, a photoelectric isolation circuit and a power amplifying circuit; two power amplifying circuits are connected with an electromagnetic deflection coil; the frequency of a clock circuit is distributed by the complicated programmable logic device; a clock used for generating various frequencies is respectively used for serial communication, control of a collecting card, and generation of frequency-variable waveforms; the industrial control computer is used for controlling the complicated programmable logic device by the serial communication circuit; the complicated programmable logic device is used for generating the digital quantity of two waveforms under the triggering of the clock circuit; and an amplified signal is used for driving the electromagnetic deflection coil to generate a magnetic field so as to scan the deflection of an electron beam. The device has high control accuracy for scanning the deflection of the electron beam; and a digital circuit can largely enhance the anti-disturbance capability of the device.

The present disclosure provides an integrated circuit. The integrated circuit includes a frequency detector coupled with a logic circuit; a supply voltage regulator coupled with the frequency detector and designed to provide an adaptive voltage supply to the logic circuit based on a frequency error from the frequency detector; and a substrate bias regulator coupled with the frequency detector and designed to provide an adaptive body bias voltage to the logic circuit based on the frequency error.