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A 3D NAND manufacturing method

A manufacturing method and technology of substrate structure, applied in the direction of semiconductor devices, electrical components, circuits, etc., can solve problems such as peeling, device reliability and frequency reduction, wafer scrapping, etc.

Active Publication Date: 2020-12-18
YANGTZE MEMORY TECH CO LTD
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The problem of arc discharge will directly lead to the scrapping of the wafer, resulting in a decrease in yield, and the problem of edge peeling will also lead to a decrease in the reliability and frequency of the device

Method used

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  • A 3D NAND manufacturing method
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  • A 3D NAND manufacturing method

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Embodiment Construction

[0025]Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Although the drawings show exemplary embodiments of the present disclosure, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0026]Figure 3(a)-3(g) A method of forming a 3D NAND according to an embodiment of the present invention is shown.

[0027]First, a substrate structure is provided, which has a substrate 300, a stepped structure 310 formed by an ON stack formed on the substrate 300, a high density plasma (HDP) deposition layer 320 and a TEOS layer 330 covering the stepped structure 310.

[0028]As shown in FIG. 3(a), after the steps are formed, ...

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Abstract

Provided is a method for manufacturing 3D NAND, comprising the following steps: before performing polysilicon channel etching; depositing and forming a barrier layer (320) and a filling layer (330); coating a negative photoresist layer; using a negative photoresist WEE (wafer edge exposure) process, retaining the negative photoresist on the edge of the wafer; etching to remove the filling layer exposed by the negative photoresist, where the etching selectivity ratio of the barrier layer and the filling layer is large, so that the barrier layer acts as an etching barrier layer; removing the remaining filling layer (331) by using a CMP process, wherein the barrier layer (320) serves as a CMP barrier layer; removing the barrier layer (320). Preferably, the barrier layer is a SiN layer deposited by PECVD, and the filling layer is a silicon oxide layer deposited by HDP. Through this process, the arc and peeling defects at the edge of the wafer in the 3D NAND process can be avoided, and the yield of the wafer can be improved.

Description

Technical field[0001]The invention relates to a 3D NAND manufacturing method, in particular to a novel process for avoiding the problems of edge discharge and peeling of a wafer.Background technique[0002]As a technology of stacking data units, 3D NAND flash memory has increased the storage capacity and reduced the storage cost of each data bit, and has become a mainstream storage technology. Among them, vertically stacked 3D NAND flash memory is a common device stacking method.[0003]The conventional 3D NAND flash memory core includes a substrate 100 including a central area (AA) and a peripheral area (PA). The manufacturing method includes: forming a peripheral gate structure in the peripheral area; forming an ON stack layer in the central area, by photolithography / etching The step structure 110 is formed by etching, and the photolithography etching can adopt the trim / Etch method; perform a high-density plasma deposition (HDPdeposition) layer 120 and a TEOS deposition layer 130 on t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/1157H01L27/11578
CPCH10B43/35H10B43/20
Inventor 袁彬周成龚睿赵治国唐兆云霍宗亮
Owner YANGTZE MEMORY TECH CO LTD
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