A memory access method and computer system

A computer system and memory access technology, applied in the field of communication, can solve the problems of large access delay and low access efficiency, and achieve the effect of reducing memory access delay and improving memory access efficiency.

Active Publication Date: 2020-06-26
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Since the memory controller needs to send an activation command to process each access request, the access delay in the memory access process is large and the access efficiency is not high

Method used

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  • A memory access method and computer system
  • A memory access method and computer system
  • A memory access method and computer system

Examples

Experimental program
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Embodiment Construction

[0031] An embodiment of the present invention provides a memory access method, a memory controller and a computer system for reducing memory access delay.

[0032] In order to enable those skilled in the art to better understand the solutions of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only It is an embodiment of a part of the present invention, but not all embodiments.

[0033] The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and not necessarily Used to describe a specific sequence or sequence. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments described her...

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PUM

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Abstract

A memory access method, used to decrease memory access latency, said method comprising: a memory controller acquiring a second access request in an access queue (408), said access queue at least comprising a first access request and said second access request, the second access request comprising a second row address and a second column address; the memory controller determining that the second row address hits a second address range (409), the row indicated by a third row address in the second address range being in an activated state, and the second row address and the third row address being different; the memory controller sending a second access instruction to a control circuit according to the second access request (410), the second access instruction including the second column address and a second row offset, the second row offset being the offset amount between the second row address and the third row address.

Description

technical field [0001] The invention relates to the communication field, in particular to a memory access method and a computer system. Background technique [0002] In an existing computer system, the memory is usually composed of Dynamic Random Access Memory (DRAM, Dynamic Random Access Memory). In the case of a memory composed of a non-volatile memory (NVM), the NVM is connected to a standard Double Data Rate (DDR) bus. In NVM, there is a part of the register space that can be accessed by the memory controller through the Double Data Rate (DDR) bus. The register space usually includes: configuration register space, request completion queue, request queue, data buffer, etc. [0003] In the case of NVM as a memory, in the process of accessing the NVM by the memory controller, the access method of accessing the DRAM is usually used to access the registers of the NVM. Specifically, during the access process, the memory controller needs to send row activation commands and co...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/06
CPCG06F12/06
Inventor 邹乔莎肖世海杨伟
Owner HUAWEI TECH CO LTD
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