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Semiconductor structure, forming method thereof and SRAM

A technology of semiconductor and gate structure, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., can solve the problems of poor overall performance of semiconductor devices, achieve improved read redundancy, improve overall performance, and improve performance Effect

Active Publication Date: 2018-06-05
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, the performance of the static random access memory in the semiconductor device formed by the prior art needs to be further improved, so that the overall performance of the semiconductor device is relatively poor

Method used

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  • Semiconductor structure, forming method thereof and SRAM
  • Semiconductor structure, forming method thereof and SRAM
  • Semiconductor structure, forming method thereof and SRAM

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Embodiment Construction

[0015] It can be seen from the background art that the performance of static random access memory (SRAM) in semiconductor structure needs to be improved.

[0016] For SRAM, it mainly includes a pull-up (Pull Up, PU) transistor, a pull-down (Pull Down, PD) transistor, and a transfer gate (Pass Gate, PG) transistor, and the read margin of the memory has a significant impact on the memory. Performance plays a key role. If the read redundancy performance of the memory can be improved, the performance and yield of the memory will be improved, and the overall performance of the semiconductor device will be improved accordingly. Wherein, the read redundancy of the memory is proportional to the beta ratio (betaratio), and the beta ratio is the ratio between the on-state current (Ion) of the pull-down transistor and the on-state current of the pass-gate transistor.

[0017] Therefore, increasing the on-state current of the pull-down transistor or reducing the on-state current of the pa...

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Abstract

The invention provides a semiconductor structure, a forming method thereof and an SRAM. The method comprises a step of providing a base which comprises substrate and discrete fins on the substrate, wherein the substrate includes a pass gate transistor region, a step of forming gate structures which go across the fins and cover a part of top surfaces and side wall surfaces of the fins, and a step of forming pass gate doping areas in the fins at two sides of the gate structures of the pass gate transistor region, wherein a pass gate doping area of at least one side is formed by a non-epitaxial layer mode that performs ion doping on the fins. The pass gate doping area of at least one side is formed by the non-epitaxial layer mode that performs ion doping on the fins, compared with a scheme offorming pass gate doping areas by an epitaxial layer mode at two sides, the contact resistance between a subsequent metal silicide and the pass gate doping areas is increased, thus the on-state current of a formed pass gate transistor is decreased, the SRAM beta ratio is inversely proportional to the on-state current of the pass gate transistor, and thus the read margin of an SRAM is improved.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a semiconductor structure, a forming method thereof, and an SRAM. Background technique [0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. With the development of semiconductor technology, storage devices are more widely used, and the storage device and other device regions need to be formed on a chip at the same time to form an embedded semiconductor storage device. For example, to embed the storage device in the central processing unit, it is necessary to make the storage device compatible with the embedded central processing unit platform, and maintain the specifications and corresponding electrical performance of the original storage device. [0003] Generally, the memory device needs ...

Claims

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Application Information

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IPC IPC(8): H01L29/78H01L29/06H01L27/11
CPCH01L29/0603H01L29/0684H01L29/7855H10B10/12H01L21/823418H01L21/823431H01L29/66795H01L29/41791H01L29/7851H01L27/0924H01L29/0847H01L29/165H10B99/00G11C11/4023H01L27/0886
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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