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Register generating method device for chip verification

A technology for generating devices and registers, used in instruments, special data processing applications, electrical digital data processing, etc., and can solve the problem of only being widely supported

Inactive Publication Date: 2018-06-12
SUZHOU CENTEC COMM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] In the process of chip verification, a register model needs to be established. In the existing technology, the register model is usually bound to UVM (Universal Verification Methodology, Universal Verification Methodology). Users must use UVM to build a verification environment; access through the CPU must call the corresponding Sequencer; register and memory modeling can only be widely supported, and users need to develop special registers and memories, that is, RAL (Register Abstraction Layer, register abstraction layer) is general

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  • Register generating method device for chip verification

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Embodiment Construction

[0017] The present invention will be described in detail below in conjunction with various embodiments shown in the drawings. However, these embodiments do not limit the present invention, and any structural, method, or functional changes made by those skilled in the art according to these embodiments are included in the protection scope of the present invention.

[0018] An embodiment of the present invention provides a register generation method for chip verification, such as figure 1 shown, including the following steps:

[0019] Step 101: receiving design specifications for registers;

[0020] Step 102: Parse the design specification and generate registers.

[0021] Preferably, said generating registers includes: generating registers conforming to SystemVerilog specifications.

[0022] Preferably, the following steps are also included: compiling the register;

[0023] Preferably, the following steps are also included: start the simulation, call the model initialization...

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Abstract

The invention provides a register generating method for chip verification. The method comprises the following steps that a design specification for the register is received; the design specification is analyzed, the register is generated, and thereby the register irrelevant to a verification platform can be generated according to the design specification.

Description

technical field [0001] The invention relates to the technical field of chip verification, in particular to a register generation method and device for chip verification. Background technique [0002] In the process of chip verification, a register model needs to be established. In the existing technology, the register model is usually bound to UVM (Universal Verification Methodology, Universal Verification Methodology). Users must use UVM to build a verification environment; access through the CPU must call the corresponding Sequencer; register and memory modeling can only be widely supported, and special registers and memories need to be developed by the user, that is, RAL (Register Abstraction Layer, register abstraction layer) is universal. [0003] Therefore, designing a platform-independent method that can automatically generate registers has become an urgent problem to be solved. Contents of the invention [0004] The object of the present invention is to provide a ...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/367G06F30/398
Inventor 唐飞陈曦常志恒
Owner SUZHOU CENTEC COMM CO LTD
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