Method and device for selecting test graphs and method and device for building photolithography models

A technology for testing graphics and lithography, applied in the directions of instrumentation, design optimization/simulation, calculation, etc., can solve the problems of difficult convergence, reduced accuracy, and reduced modeling efficiency in model construction, so as to avoid difficult convergence or reduce accuracy, The effect of avoiding the increase of calculation time and improving the accuracy of the model

Active Publication Date: 2018-06-12
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

[0005] From the perspective of modeling, more test patterns can improve the accuracy of the model. From this point of view, in the process of building the lithography model, it is necessary to select as many test patterns as possibl

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  • Method and device for selecting test graphs and method and device for building photolithography models
  • Method and device for selecting test graphs and method and device for building photolithography models
  • Method and device for selecting test graphs and method and device for building photolithography models

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Embodiment Construction

[0059] In the process of constructing the existing lithography model, the selection of the test pattern is generally selected from the already designed initial test pattern by using the existing experience. This method of relying on experience to select test patterns has the problems of slow modeling efficiency and inaccurate lithography models. Moreover, with the continuous improvement of integrated circuit integration, process nodes continue to advance, and feature sizes are getting smaller and smaller. The test patterns are becoming more and more complex. It is impossible to select the test patterns for lithography model construction from the initial test patterns only by relying on experience alone, so as to improve the modeling efficiency of lithography models and the accuracy of lithography models. Accuracy.

[0060] In view of this, the embodiment of the present application provides a method for selecting a test pattern. After obtaining the initial test pattern, the sel...

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Abstract

An embodiment of the invention discloses a method and a device for selecting test graphs. The method includes designing initial test graphs according to design rules, actual circuit layout and/or random layout; optically simulating the initial test graphs according to simplified models to obtain distribution of the initial test graphs in preset parameter value ranges; selecting key test graphs from the initial test graphs according to the distribution of the initial test graphs in the preset parameter value ranges. The key test graphs are used for calibrating parameters during photolithographymodel building. The method and the device have the advantages that the test graphs selected by the aid of the method can be used for building photolithography models, and accordingly the model building efficiency and the accuracy of the photolithography models can be improved. The invention further relates to a method and a device for building the photolithography models.

Description

technical field [0001] The present application relates to the technical field of integrated circuit manufacturing, and in particular to a method and device for selecting a test pattern. In addition, the present application also particularly relates to a method and device for constructing a photolithography model. Background technique [0002] The lithography model is the basis of optical simulation, mainly including optical parameters, photoresist parameters, etc., which reflect the process of optical transmission, photochemical reaction and physical reaction in the lithography process. [0003] In the process of building a lithography model, the selected test pattern has a great influence on the modeling efficiency and the accuracy of the final model. Moreover, with the continuous improvement of the integration level of integrated circuits, the process nodes continue to advance, the feature size is getting smaller and smaller, and the test patterns are becoming more and mor...

Claims

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Application Information

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IPC IPC(8): G06F17/50
CPCG06F30/20G06F30/39
Inventor 赵利俊韦亚一董立松张利斌
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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