current limiting circuit

Abstract

The invention discloses a current limiting circuit applied to a power circuit including a power transistor. The current limiting circuit generates a reference voltage signal including m intervals according to an output voltage and an input voltage of the power circuit and n different reference voltages and thus generates limiting current comprising m intervals, wherein n is a positive integer larger than or equal to 1, the n different reference voltages are increased in sequence. According to the current limiting circuit, a condition that the power of the power transistor tends to be constantis ensured while a current flowing through the power transistor is limited, the design cost is reduced, and the applicable range is expanded.

Description

technical field [0001] The invention relates to the field of electronic technology, in particular to a current limiting circuit. Background technique [0002] With the rapid development of semiconductor technology, it is necessary not only to ensure the stability of the output voltage, but also to improve the protection of electronic switches (such as MOS tubes) during the circuit design process. The current limiting method is usually used to protect the MOS tube, and the common current limiting control method is to limit the current through current limit foldback (Current Limit Fold Back). [0003] Figure 1(a) is an external MOS current limiting control circuit, using an external current detection resistor R SNS Realize the detection of the output current. When the load is relatively light, the output voltage V OUT exceeds the reference voltage V REF When, the selector inside the chip will V LMT1 access circuit (V LMT2 <V LMT1 ), making R through the inner loop S...

AI Technical Summary

Problems solved by technology

The solid line in the two figures is the constant power control mode, and the dotted line is the foldback current-limiting control mode of the prior art. It can be seen from the figure that the limit current, power The normalized curve does not fit the constant power control mode very well. If V LMT2 Larger, there will be a larger power point, if V LMT2 is relatively small, the output voltage V OUT The driving ability of the relatively small circuit is too poor

At present, digital ACD is usually used to sample V IN , V OUT , I OUT To achieve constant power control, and use the processor to calculate power consumption, the cost of the chip is very high, and the scope of application is small

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