A High Speed ​​Clock Receiver Circuit with Programmable Adjustment of Clock Cross Point

Abstract

The invention relates to a high-speed clock receiving circuit for programmable clock cross point adjustment, which comprises a cross point adjustment circuit, a cross point detection circuit, a cross point configuration circuit and a buffer circuit. The cross point adjustment circuit receives the high-speed differential input clock signal and adjusts the differential clock cross point according to the control signal Vc generated by the feedback loop; the buffer circuit converts the CML clock signal into a standard CMOS clock signal and enhances the clock signal drive capability; the first cross point detection The circuit and the second cross point detection circuit respectively detect the cross point of the clock signal at the input and output ends of the buffer, and generate cross point indication signals Vcp and Vcn; the cross point configuration circuit generates a cross point according to Vcp, Vcn and configuration signal A The control signal Vc used by the dot adjustment circuit. The invention can realize the adjustment of the high-speed differential clock cross point in the full voltage range by inputting the code word, and flexibly adjusts between them, meets various application requirements such as a data converter circuit, and realizes a high-performance clock receiving circuit.

Description

technical field [0001] The invention relates to a high-speed clock receiving circuit with programmable adjustable clock cross point, belonging to the technical field of high-speed clock receiving. Background technique [0002] High-speed clock signals are usually used in military equipment such as wireless communication equipment and radar, and high-performance high-speed clock receiving circuits are crucial. The intersection point of the differential clock signal directly affects the effect of the high-speed clock receiving circuit receiving the clock, and even affects the performance of some circuits. For example, the unreasonable intersection point of the differential switch signal of the current-mode digital-to-analog converter will seriously restrict the improvement of the dynamic performance of the converter. Due to the influence of non-ideal factors such as noise and mismatch in the transmission process, the intersection point of the high-speed differential clock gen...

AI Technical Summary

Problems solved by technology

For example, the unreasonable intersection point of the differential switch signal of the current-mode digital-to-analog converter will seriously restrict the improvement of the dynamic performance of the converter.

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