Providing scalable dynamic random access memory (DRAM) cache management using tag directory caches

Abstract

Providing scalable dynamic random access memory (DRAM) cache management using tag directory caches is provided. In one aspect, a DRAM cache management circuit is provided to manage access to a DRAM cache in a high-bandwidth memory. The DRAM cache management circuit comprises a tag directory cache and a tag directory cache directory. The tag directory cache stores tags of frequently accessed cachelines in the DRAM cache, while the tag directory cache directory stores tags for the tag directory cache. The DRAM cache management circuit uses the tag directory cache and the tag directory cache directory to determine whether data associated with a memory address is cached in the DRAM cache of the high-bandwidth memory. Based on the tag directory cache and the tag directory cache directory, theDRAM cache management circuit may determine whether a memory operation can be performed using the DRAM cache and / or a system memory DRAM.

Description

[0001] priority claim [0002] This application requires filing on January 21, 2016 and is entitled "PROVIDING SCALABLE DYNAMICRANDOM ACCESS MEMORY (DRAM) CACHE MANAGEMENT USING TAG DIRECTORY CACHES), the contents of which are incorporated herein by reference in their entirety. [0003] This application is also required to be filed on June 24, 2016 and is entitled "PROVIDING SCALABLE DYNAMICRANDOM ACCESS MEMORY (DRAM) CACHE MANAGEMENT USING TAG DIRECTORY CACHES), the contents of which are incorporated herein by reference in their entirety. technical field [0004] The techniques of this disclosure relate generally to dynamic random access memory (DRAM) management, and in particular, to management of DRAM cache memory. Background technique [0005] The advent of die-stacked integrated circuits (ICs) consisting of multiple stacked dies interconnected vertically has enabled the creation of die-stacked dynamic random access memories (DRAMs). Die-stacked DRAM can be used to i...

AI Technical Summary

Problems solved by technology

While the latter practice minimizes SRAM usage, any incorrect predictions will result in data being read from system memory DRAM

Reads to system memory DRAM incur additional access latency, which may negate any performance improvement from using DRAM cache

Still other practices may require very large data structures stored in system memory DRAM in order to keep track of cached data

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