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Data processing

A technology for data processing devices and processor cores, which is applied in the fields of electrical digital data processing, program control design, instruments, etc., and can solve the problems that compilers cannot use vector expressions, etc.

Active Publication Date: 2018-08-31
SWARM64
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, programmers or source language compilers often cannot express the operations to be performed using vectors, and in many cases utilize only one lane of the vectorized execution unit

Method used

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Embodiment Construction

[0117] Before discussing the embodiments in more detail, an overview will first be provided. Embodiments provide efficient scheduling of processing of program code by processor cores. The instructions supported by a processor fall into one of two types, categories, or classes. The first class of instructions are faster executing instructions or low latency instructions. These low-latency instructions are instructions that can be processed, and the result of that processing is immediately available to any subsequent instruction (in other words, the result is guaranteed to be available as input for a subsequent instruction). The second class of instructions are slower executing instructions or high latency instructions. The results of these high-latency instructions may not be available as input to subsequent instructions because those instructions take longer to execute (in other words, there is no guarantee that their results will be available as input to subsequent instruct...

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Abstract

Data processing apparatus, data processing methods, a method and a computer program product are disclosed. The data processing apparatus comprises: a processor core operable to execute sequences of instructions of a plurality of program threads, said processor core having a plurality of pipeline stages, one of said pipelined stages being an instruction schedule stage having scheduling logic operable, in response to a thread pause instruction within a program thread, to prevent scheduling of instructions from that program thread following said thread pause instruction and instead to schedule instructions from another program thread for execution within said plurality of pipeline stages. In this way, the data processing apparatus does not need to determine whether dependencies exist betweeninstructions or not, but instead can simply continue issuing instructions until a pause instruction is received. This significantly simplifies the operation of the processor core.

Description

technical field [0001] The present invention relates to a data processing device, a data processing method, a method and a computer program product. Background technique [0002] A conventional microprocessor issues and executes individual instructions one after the other. These instructions typically perform a single operation on two scalar values, producing a result. The single-issue variant issues one instruction per clock cycle, which is then processed by one of the execution units. Execution units typically include at least adders, multipliers, load / store units, and branch units. Although the operating system may create the illusion of multiple concurrent threads by configuring the processor to switch between threads at regular intervals, a processor like this runs only one program thread at a time and belongs to a group of single-threaded processors. Despite the low performance of these types of processors, they also have a small silicon area, so the performance per...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/38
CPCG06F9/3009G06F9/3851Y02D10/00G06F9/30076G06F9/3838
Inventor 埃温·利兰
Owner SWARM64