FPGA implementation method and device of a general quasi-cyclic ldpc code encoder

Abstract

The invention discloses a method and device for realizing a general-purpose quasi-cyclic LDPC code encoder. The invention generates the number of cyclic blocks in the non-unit matrix part of the matrix, the dimension of the cyclic block, the code length, the code rate, the system clock and The requirement of encoding rate is compromised and quantitatively calculated, and the method of obtaining the parallel degree of partly parallel encoding modules. This method not only has the versatility of calculation and configuration, but also can achieve a good compromise between the encoding rate and the amount of resources consumed, thereby overcoming the slow encoding rate of the serial input encoder and the hardware consumption of the fully parallel input encoding circuit. Too many resources are not conducive to the rational use of resources, and the logical connection of the two-step encoding circuit is complicated.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a method and device for realizing a general-purpose quasi-cyclic LDPC code encoder with FPGA. Background technique [0002] Among various current channel coding schemes, low-density parity check codes (LDPC) are one of the most promising channel coding schemes that are closest to the Shannon limit. The LDPC code was proposed by Gallager in 1962, but it did not receive much attention in the next 35 years. Until 1981, Tanner represented the LDPC code with a graph, which was called the Tanner graph. In the 1890s, LDPC codes were finally rediscovered by Mackay, Luby and other scholars, and research in related directions was done. Mackay expressed the parity check matrix of LDPC codes with Tanner graph, and found that LDPC codes based on belief propagation iterative decoding (BP) is a kind of channel coding whose performance is close to the Shannon limit, and its decoding com...

AI Technical Summary

Problems solved by technology

The hardware implementation complexity of the serial input encoding circuit is proportional to the number of check bits, and the consumption of the encoding clock is proportional to the number of information bits, which is difficult for high information rates.

The parallel input encoding circuit consumes much more hardware resources such as registers than the serial input encoding circuit, which is not conducive to the rational use of resources

Two-stage encoding circuit, which consumes more trigger resources and less logic resources, but the logic connection is complex

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