A communication method based on fpga and fpga controller and usb adapter
A communication method and controller technology, applied in the field of communication, can solve the problems of complex communication adaptation and application cost of peripheral circuits, and achieve the effects of low application cost, avoiding mutual influence, and reducing use cost
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Embodiment 1
[0021] Embodiment 1: FPGA controller for communication, such as figure 1 Shown.
[0022] In this embodiment, a USB controller 101 and an FPGA controller 102 are sequentially connected between the USB master device D1 and the USB slave device D2, wherein the USB controller 101 and the USB master device D1 are connected by USB communication, The FPGA controller 102 and the USB slave device D2 are connected by USB communication or IO communication, and the USB controller 101 and the FPGA controller 102 are connected by bus.
[0023] In this embodiment, the USB controller 101 and FPGA controller 102 constitute a USB adapter. The former is used to process the underlying USB protocol, and the latter is used to process the driver layer USB protocol. The two communicate and connect and work together, which greatly enhances The hardware acceleration effect during USB communication is improved.
[0024] In this embodiment, the USB controller 101 has a functional component for processing the u...
Embodiment 2
[0027] Embodiment 2: FPGA-based communication method, such as image 3 Shown.
[0028] At the beginning of the communication, the USB host device D1 sends payload data to the USB controller 101, and the USB controller 101 performs verification processing on the payload data after receiving it. The verification processing includes data packet flag identification, underlying USB protocol authentication and data packet Then, the USB controller 101 sends the checked and processed payload data to the FIFO module 1021. Thereafter, the FPGA controller 102 will receive the load data and process the data.
[0029] In this embodiment, the provided communication method is a part of the communication mechanism between USB master and slave devices, which mainly implements the processing function of the driver layer USB protocol, which will be combined below figure 1 The communication method is described in detail, and the communication method includes the following steps:
[0030] 201. The FIFO ...
Embodiment 3
[0049] The third embodiment, the operation flow chart of the state machine module, such as Figure 4 Shown.
[0050] Since the state machine module 1022 is the control component of the FPGA controller 102, this embodiment will take the active control process of the state machine module 1022 as the main line to describe in detail the processing process of the FPGA controller on the load data, including four processing steps , Respectively:
[0051] 301. The state machine module 1022 enters the "idle" state.
[0052] This state is the initial state of the state machine module 1022. The state machine module 1022 will identify the data storage state in the FIFO module 1021, and the identification method may be an active method or a passive method.
[0053] In this state, the state machine module 1022 will control the FIFO module 1021 to enable its write operation, so as to obtain the load data from the USB controller 101 at any time.
[0054] 302. The state machine module 1022 enters the ...
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