Memory device and command reordering method

A memory and reordering technology, which is applied in the direction of static memory, digital memory information, information storage, etc., can solve the problem of insufficient utilization of DDR4 parallel computing and processing capabilities, low utilization of DDR4 bandwidth, and page table conflicts without optimized order order and other issues to achieve the effect of improving bandwidth utilization, reducing the probability of page table conflicts, and optimizing bandwidth performance

Active Publication Date: 2022-03-04
VIA ALLIANCE SEMICON CO LTD
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  • Summary
  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

However, the existing command scheduling mechanism does not make full use of the parallel processing capability of DDR4 between memory banks, and does not optimize the order of commands within the bank to reduce page table conflicts, thus making the bandwidth utilization of DDR4 low rate

Method used

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  • Memory device and command reordering method

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Embodiment Construction

[0018] As used throughout the present specification, including the claims, the term "coupled (or connected)" may refer to any means of connection, direct or indirect. For example, if it is described that a first device is coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be connected to the second device through other devices or certain A connection means indirectly connected to the second device. In addition, wherever possible, elements / components / steps using the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements / components / steps using the same symbols or using the same terms in different embodiments can refer to related descriptions.

[0019] figure 1 It is a schematic diagram of a circuit block of a memory device according to an embodiment of the present invention. Please refer to figure 1 , the memory device ...

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Abstract

A memory device and command reordering method, the memory device includes a controller and at least one memory. The controller is used for providing multiple access commands and performing a command reordering method for the multiple access commands. The command reordering method includes: a hierarchical step, selecting at least one command with the same hierarchical address as the previous scheduling command from the access command as at least one first candidate command; a library level step, selecting from at least one first candidate command At least one command with a bank address different from that of the previous scheduling command is used as at least one second candidate command; and a command is selected from the at least one second candidate command as the current scheduling command. The invention can reduce the probability of page table conflict in the library, effectively improve the bandwidth utilization rate of the memory, and the like.

Description

technical field [0001] The present invention relates to an electronic device, and more particularly to a memory device and its command reordering method. Background technique [0002] In the existing fourth generation double data rate synchronous dynamic random access memory (Double Data Rate Fourth Generation Synchronous Dynamic Random Access Memory, DDR4 SDRAM) technology, its command scheduling mechanism includes a non-reordering mechanism. The method of not reordering directly dispatches the command from the first position of the command queue (queue), and then converts the command into the corresponding DDR4 command format and transmits it to the memory. However, the existing command scheduling mechanism does not make full use of the parallel processing capability of DDR4 between memory banks, and does not optimize the order of commands within the bank to reduce page table conflicts, thus making the bandwidth utilization of DDR4 The rate is lower. Contents of the inv...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
CPCG06F3/0604G06F3/0658G06F3/0659G11C11/4076G11C11/408G11C8/12G06F13/1626G06F3/0673
Inventor 金杰
Owner VIA ALLIANCE SEMICON CO LTD
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