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A method of building a reference model with python to improve the efficiency of an automated verification platform

A technology of automatic verification and reference model, applied in the field of chip verification, to achieve the effect of improving verification efficiency and excellent development efficiency

Active Publication Date: 2021-09-21
BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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Problems solved by technology

[0006] The technical problem solved by the present invention is to solve the problem of calling the Python reference model by the SystemVerilog verification platform by encapsulating the Python function with the C function for the current complex chip verification, and proposes a method of using Python to build a reference model to improve the efficiency of the automated verification platform method, greatly improving the verification efficiency

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  • A method of building a reference model with python to improve the efficiency of an automated verification platform

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Embodiment Construction

[0048] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0049] The specific implementation steps will be described below in conjunction with the verification of the PKE (Public Key Engine) coprocessor.

[0050] figure 1 It is a specific implementation flow chart. The first step and the third step are to define the interface specification of the Python function and the definition of the C interface specification respectively. Since PKE designs 2048-bit long integer operations, but the basic variable of the C program is only 64-bit long (unsigned long integer), so For transfer parameters larger than 64 bits, the input variables from C to Python and the output variables from Python to C can only be compound types composed of 64-bit long variables. Specifically, it is a tuple type consisting of multiple 64-bit integers on the Python side, and a PyTuple type on the C side.

[0051] The seventh step is...

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Abstract

The invention discloses a method for establishing a reference model by using Python to improve the efficiency of an automatic verification platform. In the present invention, the C program is used as the middle layer, the C program can call the Python reference model through the C / Python API, and then the C interface program of the middle layer is called through the SystemVerilog DPI, thereby realizing the purpose of the SystemVerilog verification platform calling Python. The invention enables the reference model to be written in the Python language, and the Python reference model can be called dynamically in real time in the verification platform. There are many advantages in using Python language to develop programs, especially when complex algorithms such as long integer calculations have very high efficiency. This method solves the problem of interaction between SystemVerilog language and Python language, so that Python programs can be used as a reference model in the verification platform, greatly improving The efficiency and quality of verification are improved, and the cost of verification is reduced.

Description

technical field [0001] The invention relates to chip verification technology, in particular to a method for establishing a reference model with Python to improve the efficiency of an automatic verification platform. Background technique [0002] With the increasing scale and complexity of chip design, chip verification becomes more and more difficult. In the verification work, many reference models need to be written, and some reference models have high algorithm complexity, especially the reference model corresponding to the algorithm coprocessor. [0003] Traditional reference models are usually written in C language, etc., and the development efficiency of reference models written in C language is low. When it comes to long integer operations, developing a reference model in C language requires a large array to represent long integers, and issues such as carry transfer need to be considered during operations. Therefore, a more efficient and concise reference model devel...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F8/20G06F8/35
CPCG06F8/20G06F8/35
Inventor 任志强
Owner BEIJING CEC HUADA ELECTRONIC DESIGN CO LTD
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