FPGA-based implementation method of multi-path high-speed filter

Abstract

The invention particularly relates to an FPGA-based implementation method of a multi-path high-speed filter. The method comprises: step A, an input signal s(n) is processed by serial-to-parallel conversion to obtain M paths of signals S0, S1, ...,SM-1; step B, the M paths of signals after serial-to-parallel conversion are divided into M parts, wherein each path has M paths of signals; step C, M<2>paths of signals of all M parts are delayed by P units and delay data are outputted, wherein the P=N / M and the N expresses the filter coefficient number; step D, for each part of M paths of signals,the extracted delay data are multiplied by the corresponding filter coefficients and accumulation is carried out; step E, the M result data of the M parts are outputted according to a sequence, so that an output signal of a current time is obtained. A serial FIR filter is designed to be a multi-path one, the pre-stage inputted M-path signals are divided into the M parts with uniform sampling delays, multiplication and adding are carried out on each path and then result data are outputted, and the M paths of outputs of the M parts are outputted and combined to obtain the output of the multi-path high-speed filter. Therefore, the real-time continuity of the input and output is realized; and the operation becomes convenient.

Description

technical field [0001] The invention relates to the technical field of digital signal processing, in particular to an FPGA-based multi-channel high-speed filter realization method. Background technique [0002] FIR (Finite Impulse Response) filter is a finite-length unit impulse response filter, also known as a non-recursive filter. It is the most basic component in a digital signal processing system. The linear phase-frequency characteristics, and its unit sampling response is finite, so the filter is a stable system. FIR filters are widely used in communication, image processing, pattern recognition and other fields. [0003] With the development of technology, the chip sampling rate is getting higher and higher, generally at GHz, while the coefficient clock rate of FPGA is relatively low, generally not exceeding 400MHz. When the signal sampling rate is much higher than the FPGA operating clock frequency, due to chip limitations, it is no longer possible to use the tradi...

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Problems solved by technology

Therefore, to implement a FIR filter with a higher computing rate in the FPGA, only a parallel structure can be used to reduce the operating frequency of the FPGA.

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