AMC-framework-based Rapid IO system integration application verification system and method

Abstract

The invention discloses an AMC-framework-based Rapid IO system integration application verification system and method. 1601P board interior inter-device Rapid IO interconnection design, AMC inter-single-board interconnection design, interconnection design with Rapid IO interface boards of devices of different types, and system integration design such as multi-node networking communication throughswitch are included. By means of the system and method, the problems that two nodes between devices inside a single board during traditional Rapid IO verification cannot be achieved, 1X / 4X working does cannot be flexibly configured, and multi-node networking communication cannot be achieved are solved, coverage of two-node interconnection application can be ensured, Rapid IO inter-board interconnection application between devices of different types can be achieved, and system integration application verification of multi-Rapid-IO-node networking communication can be completed, the Rapid IO design function and performance in system integration are comprehensively verified, and design examples are provided for follow-up application and popularization.

Description

technical field [0001] The invention relates to the field of integrated circuit system integration application verification and development, in particular to a RapidIO system integration application verification system and method based on AMC architecture, which can fully verify the design function of RapidIO. Background technique [0002] 1601P is the initial sample chip of the nuclear high-level project "Massive Information Processor". It is a normal multi-core processor that integrates multiple functional modules or high-speed communication interfaces such as PPC core, network on chip, DDR and RapidIO. The 4-channel 4X RapidIO high-speed communication interface integrated in 1601P can be used in single-channel 4X mode, single-channel 1X mode, and can also work in 1X / 4X mixed mode, which increases the flexibility of system integration. [0003] However, in the previous single-chip application verification, the PCB board interconnection between 1601P and another controller ...

AI Technical Summary

Problems solved by technology

[0004] First of all, the interconnection of two chips through RapidIO can only verify the most basic design function of RapidIO communication, and cannot flexibly configure the 1X / 4X compatible working mode and 1X / 4X mixed working mode of RapidIO, which is the most ideal application condition in system integration applications , cannot cover the design functions of RapidIO, nor can it strictly assess the design performance indicators of RapidIO, and cannot fully expose possible design flaws in system integration

Secondly, the original intention of RapidIO design is to achieve high-speed interconnection between boards. The intra-board interconnection between chips cannot reflect the general usage in subsequent system integration, and has little reference value for system integration applications of chips.

Finally, the interconnection between chips is just a simple communication between two nodes, and it is impossible to verify the system integration application where multiple RapidIO nodes are networked through a switch

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