Method and device for implementing cache data consistency based on distributed finite directory

Abstract

The invention discloses a cache data consistency realization method and device based on a distributed limited directory. The invention responds to the request of the corresponding processing unit PE X through the private cache PCache X, and sends a request to the corresponding processing unit PE X when the request misses or the data is written back. The host DDCU X sends a data read and write consistency request transaction, and the host DDCU X discards the packet and enters the flow control mode when encountering a resource conflict when processing the request transaction, and PCache X resends the discarded packets one by one based on the contract principle , until the resource conflict is resolved, exit the flow control mode and enter the normal pipeline operation mode. The present invention can solve the problem of starvation of request transactions caused by directory self-replacement blocking the work pipeline, and at the same time provide strict execution sequence guarantees to ensure that in a distributed environment, data dependencies are not destroyed, and data dependencies between request transactions can be completely maintained , and ensure that the request transactions issued by multiple cores can be executed in a fair and coordinated manner, thereby improving the reliability and scalability of many-core processors.

Description

technical field [0001] The present invention relates to a multi-core processor architecture, in particular to a method and device for implementing cache data consistency based on a distributed limited directory, which is used to solve the problem of a directory-based high-speed cache (Cache) consistency protocol when the capacity of the directory memory is limited. Directory self-replacement clogged the work pipeline and caused request transaction starvation. Background technique [0002] The common implementation method of many-core microprocessors is isomorphic integration, that is, integrating multiple mature general-purpose processing cores with the same structure and powerful functions. Intel has integrated 32 processor cores in the Skylake-EP Xeon E5 chip. AMD has integrated 16 processor cores in the Ryzen Threadripper processor. Phytium series server chips integrate 16 to 64 processor cores. Such as figure 1 As shown, these processor chips integrate multi-level Ca...

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention: Aiming at the above-mentioned problems in the prior art, a method and device for implementing cache data consistency based on a distributed limited directory are provided to solve the problem of starvation of request transactions caused by directory self-replacement blocking the work pipeline, At the same time, it provides a strict execution order guarantee to ensure that in a distributed environment, data dependencies are not destroyed, data dependencies between request transactions can be completely maintained, and request transactions sent by multiple cores can be executed in a fair and coordinated manner, thereby improving publicity. Core Processor Reliability and Scalability

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