A kind of power device and its manufacturing method
A technology for power devices and manufacturing methods, applied in semiconductor devices, electric solid state devices, electrical components, etc., can solve problems such as poor product reliability, increase device area and manufacturing cost, reduce packaging manufacturing costs, and improve product quality. Reliability, effect of shrinking device area
Inactive Publication Date: 2021-02-26
眉山国芯科技有限公司
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Problems solved by technology
[0005] At present, the common method of protecting semiconductor devices is to connect transient voltage suppressors to semiconductor devices, which increases the device area and manufacturing cost, and the product reliability is not good.
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[0050] The invention will be described in more detail below with reference to the accompanying drawings. In the various figures, the same elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. Also, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.
[0051] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region.
[0052] If the purpose is to describe the situation directly on another layer or another a...
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The invention provides a power device and a manufacturing method thereof, comprising the following steps: a substrate of a first conductivity type; A first epitaxial layer of a first conductivity typeformed on an upper surface of the substrate; An antistatic structure comprising a second epitaxial layer of a first conductivity type and a third epitaxial layer of a second conductivity type; A source region formed on an upper surface of the first epitaxial layer; A gate silicon oxide layer formed on an upper surface of the first epitaxial layer; A gate polysilicon layer formed on an upper surface of the gate silicon oxide layer; A dielectric layer formed over the first epitaxial layer; A polysilicon channel connecting the gate polysilicon layer and the antistatic structure; A first metal layer and a second metal layer formed on an upper surface of the dielectric layer; A third metal layer formed on a bottom surface of the substrate. The invention reduces the area of the device, reducesthe manufacturing cost of the package and improves the reliability of the product.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a power device and a manufacturing method thereof. Background technique [0002] VDMOS (abbreviation of VDMOSFET, Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor, Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor) has drain and source poles on both sides of the device, allowing current to flow vertically inside the device, increasing the current density , The rated current is improved, and the on-resistance per unit area is also small. It is a power device with a wide range of uses. The gate of VDMOS controls the channel opening of the device, and the oxide layer at the gate position has poor high voltage resistance (usually <100V), and is extremely vulnerable to transient voltage surge damage, resulting in device failure. [0003] Electrostatic discharge, as well as other random voltage transients in the form of volt...
Claims
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IPC IPC(8): H01L27/02
CPCH01L27/0251
Inventor 李洪南
Owner 眉山国芯科技有限公司