Boundary spacer structure and integration

Abstract

The present disclosure relates to semiconductor structures, and more particularly, to N-P boundary spacer structures for use with FinFET devices and methods of fabrication thereof. The method includes: forming a plurality of first fin structures; forming a barrier layer between a first fin structure of the plurality of fin structures and a second fin structure of the plurality of fin structures; and forming an epitaxial material on the first fin structures , while blocking the extension of the epitaxial material onto the second fin structure at least by the barrier layer formed between the first fin structure and the second fin structure.

Description

technical field [0001] The present disclosure relates to semiconductor structures, and more particularly, to boundary spacer structures and methods of fabrication for use with FinFET devices. Background technique [0002] As technology nodes advance, a smaller and smaller space is provided between the n-EPI layer and the p-EPI layer formed on adjacent fin structures. For example, in a 7nm structure, the space for n-EPI and p-EPI is typically only about 50nm or less. This small separation can result in N-P shorts between n-EPI and p-EPI or between n-EPI and the Vdd power plane for adjacent devices. For example, during an epitaxial growth process performed on adjacent fins, the dimensions of the epitaxial growth may vary, or anomalous epitaxial growth may occur that expands beyond the mask formed on the respective fins, resulting in amalgamation of the epitaxial material. [0003] The solution to this problem is to reduce the growth time to form the epitaxial layer on the fi...

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Problems solved by technology

However, this in turn results in significantly smaller EPI volumes than desired, limiting device performance

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