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A cost-effective ECO method for chip design

A chip design and chip technology, applied in CAD circuit design, calculation, instrument, etc., can solve the problem of high remanufacturing cost, reduce chip manufacturing cost, save chip manufacturing cost, and avoid re-modification.

Active Publication Date: 2019-01-04
华大恒芯科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] Due to the additional requirements of the customer for the design or the ECO when the chip is found to have a defect (bug) after the sign-off, the function change usually requires the addition of a large number of logic gates or rewiring work, involving all layers of the chip. Re-modification, high cost of re-manufacturing

Method used

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  • A cost-effective ECO method for chip design
  • A cost-effective ECO method for chip design
  • A cost-effective ECO method for chip design

Examples

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Embodiment Construction

[0041] In the following description, the present invention is described with reference to various examples. One skilled in the art will recognize, however, that the various embodiments may be practiced without one or more of the specific details, or with other alternative and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the various embodiments of the invention. Similarly, for purposes of explanation, specific quantities, materials and configurations are set forth in order to provide a thorough understanding of embodiments of the invention. However, the invention may be practiced without these specific details. Furthermore, it should be understood that the various embodiments shown in the drawings are illustrative representations and are not necessarily drawn to scale.

[0042] In this specification, reference to "one embodiment" or "the...

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Abstract

The invention discloses a chip design engineering change command ECO method, which comprises the following steps: logic analysis being carried out on the defects existing in the chip; modifying a function code based on the logic analysis; analyzing the logical cone of the netlist, finding out the logical cone of the corresponding functional code in the netlist, realizing the code function which needs to be modified by the standard unit, and carrying on the synthesis logic expression; according to the logical cone analysis of the netlist, the netlist being modified manually, and the connectionrelation of the standard unit being modified, so as to realize the function corresponding to the modification of the function code; and verifying that the modifications are correct.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular, the invention relates to a cost-saving chip design ECO method. Background technique [0002] During the entire design process of the chip, the designer usually needs to continuously verify the design. As for the problems in the early stage of the design, the designer can solve them by modifying the Register Transfer Level (Register Transfer Level) RTL code. In the late stage of design, for example, near the final sign-off, it can be realized through the technology of engineering change order (ECO, Engineering Change Order). Since the ECO technology focuses on the specific problems of a specific link rather than starting from the entire design process, it greatly shortens the design cycle and saves design costs, which has great advantages. [0003] Due to the additional requirements of the customer for the design or the ECO performed when the chip is found to have...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/39G06F30/367
Inventor 龚永鑫廖峰沈红伟李险峰
Owner 华大恒芯科技有限公司
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