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Method and device for data access

A data access and data technology, applied in the input/output process of data processing, electrical digital data processing, memory architecture access/distribution, etc., can solve the problem of low transmission efficiency, slow access speed of shared cache devices, and data to disk array speed Slow and other problems, to avoid data loss

Active Publication Date: 2021-03-23
HUAWEI TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The way the controller converts the communication format and sends information to the shared cache device has low transmission efficiency, and the access speed to the shared cache device is slow, which in turn leads to slow speed for the host to save the data in the shared cache device to the disk array

Method used

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  • Method and device for data access
  • Method and device for data access
  • Method and device for data access

Examples

Experimental program
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Embodiment Construction

[0037] The technical solution in this application will be described below with reference to the accompanying drawings.

[0038] Such as figure 1 As shown, the storage system 100 at least includes: a host 101, a first controller 102, a second controller 103, and at least one shared cache device 104, wherein the host 101 is connected to the first controller 102 and the second controller 103 respectively , the first controller 102 and the second controller 103 are respectively connected to each shared cache device 104 in the at least one shared cache device 104 through the internal bus 105 .

[0039] Optionally, in this embodiment of the present application, the internal bus includes at least any one of the following internal buses: Quick Path Interconnect (Quick Path Interconnect, QPI) bus, Ultra Path Interconnect (Ultra Path Interconnect, UPI) bus, Super Transport ( Hyper Transport, HT) bus and Global Memory Interconnect (GlobalMemory Interconnect, GMI) bus.

[0040] The host...

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PUM

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Abstract

The present application provides a method for accessing data, which is applied to a storage system. The storage system includes a first controller, and the storage system further includes at least one shared cache device. Each of the first controller and the at least one shared cache device Two shared cache devices are connected through an internal bus, and the method is applied to the first controller, including: receiving a destination address sent by each shared cache device, where the destination address is used to indicate the address where data is to be written into the shared cache device; receiving the address carrying the data information; sending the destination address and data to the shared cache device sending the destination address, so that each shared cache device saves the data to the storage space pointed to by the destination address. By connecting the controller (for example, an example of the first controller) and the shared cache device through an internal bus, the host can access the shared cache device in a memory access manner, thereby increasing the access speed of the host to the shared cache device.

Description

technical field [0001] The present application relates to the field of data access, and more specifically, to a data access method and device. Background technique [0002] A dual-controller disk array system (referred to as a dual-controller disk array system) includes two controllers and disk arrays respectively connected to the two controllers. Wherein, the two controllers communicate through an external bus, for example, communicate through a Peripheral Component Interconnect Express (PCIE) bus. During the operation of the dual-controller disk array system, the data in one controller is synchronously backed up to the other controller. When a controller fails, the data can be restored from the other controller, so as to ensure that the data will not be lost. A disk array is formed by multiple physical hard disks, and two controllers jointly manage the disk array. [0003] An existing dual-controller disk array system also includes a shared cache device connected to the ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06
CPCG06F3/061G06F3/0619G06F3/0656G06F12/0246G06F12/084G06F2212/312G06F2212/7201G06F2212/7203G06F3/06G06F9/544G06F13/1663G06F13/1673G06F13/1684
Inventor 周超周佩青
Owner HUAWEI TECH CO LTD