Method for allocation of addresses in serial data bus system and bus node

Abstract

A bus node is capable of performing a method, for the assigning of bus node addresses to bus nodes of a serial data bus. The method is performed with the aid of bus shunt resistors (R2) in the individual bus nodes (SL1, SL2, SL3) in an assignment time period. After assigning bus node addresses to the bus nodes of the serial data bus system in the assignment time period, there follows an operatingtime period. For this purpose, the bus node comprises such a bus shunt resistor. The bus node is characterized by a bus shunt bypass switch (SL4) which, prior to assigning a bus node address to the bus node in the assignment time period is opened and which after the assignment of bus node address to the bus node in the assignment time period is closed, and which is closed in the operating time period.

Description

[0001] This application claims the benefit of German application number DE 10 2017 122 364.9 filed on September 26, 2017 and European application EP 17210851.6 filed on December 28, 2017, which applications are hereby incorporated by reference in their respective entireties . technical field [0002] The invention relates to a method for feeding an addressing current through a bus node of a serial data bus system and to a bus node for such a data bus system. [0003] The present invention generally relates to a self-testable serial data bus system and a method for assigning bus node addresses within this serial data bus with a bus node chain, or a method and a device in connection with the addressing preparation of bus nodes . Background technique [0004] Various methods for address assignment in LIN bus systems are known from the prior art. See, for example, the documents DE-B-10 2010 026 431 , DE-B-10 147 512 , EP-B-1 490 772 and US-B-9 331 866 . [0005] What all thes...

AI Technical Summary

Problems solved by technology

Third, the addressing system must be able to work with negative ground offsets

Fourth, the level on the bus splitter must be maximized, which requires as much addressing current as possible

This has a number of disadvantages: first, it results in very long rise times when there are many addressed bus nodes

This resistor has a disadvantage: it worsens the EMV characteristics with respect to standard-compliant LIN bus nodes

Images