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Circuit supporting multiple Hash algorithms

An algorithm and circuit technology, applied in the field of information security and cryptography, can solve the problems of high cost, reverse difficulty, poor versatility, etc., and achieve the effect of high clock frequency and high efficiency.

Active Publication Date: 2019-04-26
天津国芯科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] 2) Reverse Difficulty
Even if hackers steal the Hash value stored in the system, they still cannot obtain the password and cannot log in to the system
[0011] In the prior art, the hardware implementation scheme of the Hash algorithm can only implement one Hash algorithm, and multiple Hash algorithms need to be implemented through multiple hardware solutions, which has poor versatility and high cost

Method used

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  • Circuit supporting multiple Hash algorithms
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  • Circuit supporting multiple Hash algorithms

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Embodiment Construction

[0039] It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict.

[0040] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0041] This embodiment is a circuit that supports multiple hash algorithms, including MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, and SM3; this circuit supports continuous processing of a message, and also supports continuous processing of a message. Segmented processing, that is, another message can be inserted between two segments of a message for processing;

[0042] like figure 1 As shown, the circuit includes: initialization logic, constant selection logic, message processing logic, iteration logic, MUX and Hash value register array,

[0043] The initialization logic is used to complete the initialization of the Hash value register array, that...

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Abstract

The invention provides a circuit supporting multiple Hash algorithms. The circuit comprises an initialization logic, a constant selection logic, a message processing logic, an iteration logic, an MUXand a Hash value register array. The Hash algorithms supported by the design include MD5, SHA0, SHA1, SHA224, SHA256, SHA384, SHA512, and SM3. Continuous processing of one message is supported, only an iteration initial value defined by the corresponding Hash algorithm needs to be loaded into the Hash value register array before the first block of the message starts to be iterated, and then the message is processed continuously. In addition, the design also supports the segment processing of one message, the processing of another message can be inserted between two segments of one message, inthe mode, only an iteration result of the previous segment of the message needs to be loaded into the Hash value register array through the initialization logic before the iteration is started.

Description

technical field [0001] The invention belongs to the technical field of information security and cryptography, in particular to a circuit realization and design method supporting multiple Hash algorithms. Background technique [0002] Hash algorithm, also known as hash algorithm, hash algorithm, is a method of generating small numbers by operating on any file. Like fingerprints, Hash algorithm is a sign that guarantees the uniqueness of files with short information. A good Hash algorithm has the following characteristics: [0003] 1) Forward fast. Given the plaintext and the hash algorithm, the hash value can be calculated in limited time and limited resources. [0004] 2) Reverse difficulty. Given the hash value, it is difficult to inversely deduce the plaintext in finite time. [0005] 3) Input sensitive. Small changes to the original input information can make a big difference in the generated hash value. [0006] 4) Conflict avoidance. It is difficult to find two ...

Claims

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Application Information

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IPC IPC(8): H04L9/32H04L9/06
CPCH04L9/0643H04L9/3239H04L2209/12
Inventor 申云飞肖佐楠郑茳
Owner 天津国芯科技有限公司
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