Network flow processing method, apparatus and device, and storage medium

Abstract

The invention discloses a network flow processing method, apparatus and device, and a storage medium. The method comprises the following steps: when an FPGA chip detects that a target message exists in a packet receiving queue of a network controller, the target message is read; the FPGA chip determines the target packet receiving queue corresponding to the target message according to message contents of the target message, wherein the target packet receiving queue is the packet receiving queue corresponding to the target message in the FPGA chip; and the FPGA chip stores the target message inthe target packet receiving queue, and sends the target message to a target CPU core corresponding to the target packet receiving queue, so that the target CPU core performs service processing for the target message, and performs forwarding processing according to incoming interface information in a message header of the target message. A processor with a plurality of CPU cores can bring the processing performance into full play, so that the overall service processing performance of the processor is improved.

Description

technical field [0001] The present application relates to the field of network technology, in particular to a method, device, equipment and storage medium for processing network traffic. Background technique [0002] With the development requirements of technology and network, the performance requirements of the central processing unit (Central Processing Unit, CPU) are getting higher and higher during the working process of the product. To this end, CPU engineers have developed a multi-core processor, which integrates two or more CPUs in one processor, so that multiple CPUs in the processor can provide stronger load capacity together, thereby improving the processing speed. device performance. [0003] Such a multi-core processor can divide tasks to realize that thread applications can make full use of multiple CPU cores in the multi-core processor, thereby implementing more tasks within a certain period of time. Although the multi-core processor is a single chip (also kn...

AI Technical Summary

Problems solved by technology

Therefore, after the Higig header is added to the head of the message, the network controller cannot recognize the Higig header in the message sent by the switch chip, and the five-tuple behind the Higig header in the message cannot be parsed. As a result, all packets that cannot be parsed out of the quintuple will be shunted to the fixed packet receiving queue 0, which will cause the multi-queue attribute of the network controller to be unavailable, making the multi-core processor unable to achieve maximum performance

Images