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Problems solved by technology
This prior art aims to reduce warp due to lattice mismatch by sorting the concavo-convex shape of a silicon wafer as a substrate, but it is difficult to reduce the amount of warp (Warp) on the order of several hundred μm
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Embodiment 1
[0080] First, using a test silicon wafer (with no epitaxial layer formed), the initial stacking process of the 3D-NAND device, that is, "SiO 2 +SiN" film lamination process (multilayer film process) warping direction and warping amount. As the silicon wafer for the test, specifically, a p-type wafer with a very small warp (several μm) and a diameter of 300 mm was used. A silicon wafer with a resistivity of 10Ω·cm.
[0081] On the silicon wafer used in this experiment, 1 to 20 groups of "SiO 2 +SiN" film. The film forming conditions of each film are conditions that simulate the actual process. SiO 2 The film was formed with TEOS (film formation temperature: 380°C), and the SiN film was formed with reduced-pressure CVD (SiH 4 : 40 sccm, NH 3 : 2000sccm, pressure 250~300torr). The thickness of each layer is 25nm
[0082] Next, regarding the laminated "SiO 2 +SiN" film silicon wafer, the Warp after film formation was evaluated with a capacitance-type measuring device, and th...
Embodiment 2
[0096] In addition to the thickness of the epitaxial layer (h f ) is set to 10 μm, and the substrate boron doping concentration ([X]) is set to 5×10 19 atoms / cm 3 Except that, other epitaxial silicon wafers were manufactured in the same manner as in Example 1, and "SiO 2 +SiN” film. In Figure 5 The formed "SiO 2 The relationship between the number of groups of +SiN" film and the value of warp (Warp) of epitaxial silicon wafer.
Embodiment 3
[0098] In addition to the thickness of the epitaxial layer (h f ) is set to 15 μm, and the substrate boron doping concentration ([X]) is set to 3×10 19 atoms / cm 3 Except that, other epitaxial silicon wafers were manufactured in the same manner as in Example 1, and "SiO 2 +SiN” film. In Figure 5 The formed "SiO 2 The relationship between the number of groups of +SiN" film and the value of warp (Warp) of epitaxial silicon wafer.
[0099] The conditions of Examples 1 to 3 are all stacked with 16 groups of "SiO 2 +SiN” film is able to counteract the warpage conditions. In fact, as Figure 5 As shown, it can be seen that the epitaxial silicon wafers manufactured under any conditions of Examples 1 to 3 are stacked with 16 groups of "SiO 2 +SiN" film, Warp is basically 0. In addition, the "SiO 2 The three curves of the relationship between the number of groups of +SiN" film and the value of Warp are as follows Figure 5 overlap as shown.
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Abstract
The present invention pertains to a method for manufacturing a silicon epitaxial wafer, the method comprising: a step for pre-preparing a test silicon wafer, forming a multilayer film on the surface of the test silicon wafer, and measuring the warping direction and the warp W of the silicon wafer having the multilayer film formed thereon; and a step for selecting a silicon wafer, which is a substrate for forming a device, and the conditions for forming an epitaxial layer on the silicon wafer such that a warp that cancels the measured warp W is formed in the direction opposite to the measured warping direction, and under the selected conditions for forming an epitaxial layer, forming the epitaxial layer on the surface on which the multilayer film is formed on the selected silicon wafer which is a substrate for forming a device. Accordingly, provided is a method for manufacturing a silicon epitaxial wafer, the method being capable of manufacturing a silicon epitaxial wafer in which the warping that occurs when a multilayer film is formed thereon is reduced.
Description
technical field [0001] The invention relates to a method for manufacturing an epitaxial silicon wafer and a method for manufacturing a semiconductor device. Background technique [0002] As a substrate for producing a semiconductor integrated circuit, a silicon wafer produced by the CZ (Czochralski: Czochralski) method is mainly used. In recent state-of-the-art memory devices, a three-dimensional NAND flash memory is being used, which has a process of laminating multiple layers of films on a silicon wafer in order to increase capacity and reduce bit costs. In the comparative initial stage of the process, dozens of groups of "SiO 2 +SiN" film process. After lamination, there are multiple three-dimensional and complicated processes as follows: hole etching process to etch the cylindrical shape of the substrate, forming polysilicon film on the side wall, etching SiN process, In the electrode formation process, etc., performing each process in a state where the wafer is greatl...
Claims
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