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Scheduling tasks in a multi-threaded processor

A processor and thread technology, applied in multi-programming devices, electrical digital data processing, instruments, etc., can solve problems such as hardware duplication

Active Publication Date: 2019-04-30
GRAPHCORE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this requires a lot of duplication on the hardware side

Method used

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  • Scheduling tasks in a multi-threaded processor
  • Scheduling tasks in a multi-threaded processor
  • Scheduling tasks in a multi-threaded processor

Examples

Experimental program
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Embodiment Construction

[0041] figure 1 The figure shows an example of a processor 4 according to an embodiment of the present disclosure. For example, processor 4 may be one of an array of similar processor tiles on the same chip, or may be implemented on its own chip. Processor 4 includes a multi-threaded processing unit 10 in the form of a barrel-shaped thread processing unit, and local memory 11 (i.e., on the same tile in the case of a multi-tile array, or on the same tile in the case of a single-processor chip). on the chip). A barrel-threaded processing unit is a multi-threaded processing unit in which the pipeline's execution time is divided into a repeated sequence of interleaved time slots, each of which may be owned by a given thread. This will be discussed in more detail later. The memory 11 comprises an instruction memory 12 and a data memory 22 (which may be implemented in different addressable memory units or in different areas of the same addressable memory unit). Instruction memor...

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PUM

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Abstract

A processor comprises: an execution unit for executing a respective thread in each of a repeating sequence of time slots; and a plurality of context register sets, each comprising a respective set ofregisters for representing a state of a respective thread. The context register sets comprise a respective worker context register set for each of the number of time slots the execution unit is operable to interleave, and at least one extra context register set. The worker context register sets represent the respective states of worker threads and the extra context register set being represents the state of a supervisor thread. The processor is configured to begin running the supervisor thread in each of the time slots, and to enable the supervisor thread to then individually relinquish each of the time slots in which it is running to a respective one of the worker threads.

Description

technical field [0001] The present disclosure relates to the scheduling of tasks executed by different concurrent threads in a multithreaded processor. Background technique [0002] A multithreaded processor is a processor capable of executing multiple program threads concurrently with each other. A processor may include some hardware common to multiple different threads (eg, common instruction memory, data memory, and / or execution units); but to support multithreading, a processor also includes some dedicated hardware specific to each thread. [0003] The dedicated hardware includes at least a respective context register file for each of the plurality of threads that can execute at one time. When referring to a multithreaded processor, "context" refers to the program state (eg, program counter value, status, and current operand values) of a corresponding one of the threads executing concurrently with each other. The context register file refers to the corresponding set of...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/46G06F9/48
CPCG06F9/461G06F9/462G06F9/485G06F9/3888G06F9/3851G06F9/4887G06F9/30123G06F9/3009G06F9/30101G06F9/4843G06F9/4881G06F9/3885
Inventor 西蒙·克里斯蒂安·诺尔斯
Owner GRAPHCORE LTD