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Method and device for detecting asynchronous paths in timing paths for integrated circuits

A technology of integrated circuits and paths, which is applied in the field of asynchronous paths and non-volatile storage media in the detection of timing paths for integrated circuits, can solve problems such as lack of asynchronous paths, and achieve the effect of fast speed and accurate results.

Active Publication Date: 2021-05-04
厦门码灵半导体技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In order to solve the problem in the prior art that can quickly detect the asynchronous path in the timing path for integrated circuits, the present invention provides a method, device, electronic device, and non-volatile storage medium for detecting the asynchronous path in the timing path for integrated circuits, Ability to quickly identify asynchronous timing paths by traversing queries

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  • Method and device for detecting asynchronous paths in timing paths for integrated circuits
  • Method and device for detecting asynchronous paths in timing paths for integrated circuits
  • Method and device for detecting asynchronous paths in timing paths for integrated circuits

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Embodiment 1

[0063] This embodiment provides a method for detecting an asynchronous path in a timing path for an integrated circuit. Programmable Gate Array (English full name Field-Programmable Gate Array, referred to as FPGA), only integrated circuits that require the above-mentioned technical problems, can adopt the detection method provided by this embodiment, for example, storage systems, transmission systems, etc., among them There may be an asynchronous path, and the technical solution provided by this embodiment may also be used to quickly identify the asynchronous path in the timing path, and may also identify the asynchronous path. For ease of expression, SoC will be specifically explained below as an integrated circuit, and other types of integrated circuits can also be processed with reference to the same or similar technical means.

[0064] Such as figure 2 As shown, the method for detecting an asynchronous path in a timing path for an integrated circuit provided in this emb...

Embodiment 2

[0080] On the basis of the first embodiment, this embodiment further refines the situation that the detection does not belong to the asynchronous path information. in:

[0081] In a preferred implementation of this embodiment, the method for detecting an asynchronous path in a timing path for an integrated circuit further includes: outputting an error message when judging that the attribute information of the timing path corresponding to the data terminal of the current register does not include the start clock or the end clock.

[0082] In a preferred implementation of this embodiment, the method for detecting an asynchronous path in a timing path for an integrated circuit further includes: when judging that the timing path corresponding to the data terminal of the current register satisfies the timing constraint condition, outputting feedback information that there is a timing constraint condition.

[0083] Specifically, such as image 3 As shown, the method for detecting a...

Embodiment 3

[0095] This embodiment is based on embodiment one or embodiment two, combining Figure 4 , using prime time as an example of a static timing analysis tool to further explain the method of detecting asynchronous paths in the timing paths of integrated circuits; among them, primetime is a static timing analysis tool developed by synopsys, which is an independent tool of signoff. And the present embodiment is illustrated with the ARM 40 storehouse, and the register (register) in this database comprises:

[0096] Trigger: delay trigger (English full name D-type flip-flop, referred to as DFF), semi-dynamic trigger (abbreviated as SDFF), and A2SDFF type trigger);

[0097] a latch (for example, a LAT type latch);

[0098] A clock gating unit (for example, a PREICG type clock gating unit)

[0099] Among them, the name of the data terminal (data pin) is D including: DFF, SDFF, LAT;

[0100] Among them, the name of the data terminal (data pin) is A / B including A2SDFF;

[0101] Among...

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Abstract

The present invention belongs to the technical field of integrated circuit design. In order to solve the problem of lack of ability to quickly detect the asynchronous path in the timing path for integrated circuits in the prior art, the present invention provides a method, a device and a method for detecting the asynchronous path in the timing path for integrated circuits. Electronic device, non-volatile storage medium; the method includes traversing the registers in the integrated circuit design to be detected, obtaining timing path attribute information corresponding to the data end of any register, and judging whether the timing path is asynchronous based on the timing path attribute information path, and identify the timing path that belongs to the asynchronous path; wherein, if it is judged that the value of the start clock is not equal to the value of the end clock, and the timing path corresponding to the data terminal of the current register does not meet the timing constraints; then the data of the current register The timing path corresponding to the terminal is judged as an asynchronous path. Therefore, the asynchronous timing path can be quickly identified by traversing the query.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a method, device, electronic device, and nonvolatile storage medium for detecting an asynchronous path in a timing path for an integrated circuit. Background technique [0002] In the integrated circuit design and development process, all timing paths need to be constrained. For example, in the development process of a System on Chip (English full name System on Chip, referred to as SoC) type integrated circuit, all timing paths need to be constrained, and then Check whether the path meets the timing requirements with a static timing analysis tool such as Prime Time. [0003] The inventor found in the process of implementing the present invention that there are a large number of timing path violations, and it has been confirmed that many of the violations are asynchronous paths. In fact, the real asynchronous path does not require timing analysis. Usually, duri...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/28
Inventor 温建刚张敏梁梦雷武堃耿罗锋彭华
Owner 厦门码灵半导体技术有限公司