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A scanning test execution method, device and system

A technology of scanning test and execution method, applied in the direction of measuring devices, measuring electricity, measuring electrical variables, etc., can solve the problems of IP nuclear security threats and so on

Active Publication Date: 2022-01-04
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This is because, when the scan chain is inserted into the IP core circuit, malicious attackers can use the scan chain to obtain the confidential data of the circuit, for example, obtain the confidential data of the IP core circuit under the normal working state of the IP core, and use Scan chain removes confidential data, posing a threat to the security of IP cores

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  • A scanning test execution method, device and system
  • A scanning test execution method, device and system
  • A scanning test execution method, device and system

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Embodiment Construction

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0053] It should be noted that the scanning test process performed on the IP core needs to be based on the test shell proposed by the IEEE 1500 standard, which defines a general test shell hardware structure for the IP core. combine figure 1 As shown, the test shell proposed by the IEEE 1500 standard is set on the periphery of the IP core to be tested. The test shell consists of WIR (Wrapper Instruction Register, test shell instruction register), WBY (Wrapper ...

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Abstract

The present application discloses a scan test execution method, device and system, including: selecting at least one boundary register from the scan chain of the test shell as a key generation register; in the key generation stage, using the key generation register to generate a reference key ;In the key reading phase, in response to the user's write key request, read the key from the preset key reading register; the key read from the key reading register is inconsistent with the reference key When , the IP core under test is prohibited from performing a scan test; when the key read from the key read register is consistent with the reference key, the IP core under test is triggered to perform a scan test. Only when the user writes the key in the key read register and the key written in the key read register is consistent with the reference key, the scan test will be triggered, which improves the security of the scan test for the IP core sex.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, in particular to a scanning test execution method, device and system. Background technique [0002] With the enhancement of integrated chip functions and the continuous expansion of integrated scale, the testing of chips becomes more and more difficult. Therefore, in the initial stage of integrated circuit design, testability is taken as one of the design goals, that is, design for testability. In modern integrated circuits, scan test is the most popular design for testability method. The basic principle of scan test is: replace the sequential unit with the sequential unit with scan function inside the circuit, and serialize all the sequential units with scan function. Connected into a scan path, called a scan chain. The scan enable signal is used to control the state of the circuit: when the scan enable signal is valid, the sequential unit in the scan chain is controlled to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185
Inventor 冯燕陈岚
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI