Automatic generation method of variable bit width multiplier

A multiplier and variable technology, applied in the fields of instruments, electrical digital data processing, digital data processing components, etc., can solve the problems of insufficient flexible support for variable number of digits, and the configuration of pipeline stages has not been considered, and achieves a feasible solution. Configurable, flexible and universal effects

Pending Publication Date: 2019-07-05
SOUTHWEST JIAOTONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The disadvantage of this document is that it does not support enough flexibility for variable number of bits

Method used

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  • Automatic generation method of variable bit width multiplier
  • Automatic generation method of variable bit width multiplier
  • Automatic generation method of variable bit width multiplier

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Embodiment Construction

[0026] The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments. figure 1 For the quick generation flow chart of the multiplier proposed in this patent, the user creates the target folder, configures the required multiplier parameters, and then divides down step by step according to the nesting level of the multiplier listed in Table 3-4 and generates the corresponding RTL code until the divided unit is the smallest granularity unit, stop dividing, and complete the generation of the required multiplier RTL code. Specific steps are as follows:

[0027] Step 1: Create a target folder on the client side and configure the top-level multiplier parameters.

[0028] The top-level configuration file is a text file, which contains the parameters of the multiplier input by the user. These parameters need to be separated by spaces to be correctly recognized by the script. There are 9 parameters in it, and thei...

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Abstract

The invention discloses an automatic generation method of a variable bit width multiplier, which comprises the following steps: a user creating a target folder and configures parameters of a top layermultiplier; according to multiplier nesting hierarchies in the multiplier parameter configuration file of the current level, performing step-by-step downward division, and generating corresponding RTL codes; and stopping division until the divided unit is a unit with the minimum granularity, and finishing the generation work of the RTL code of the required multiplier. According to the method, theconfiguration of the pipeline series is considered, the configurability of the multiplier is realized, and the designed multiplier is high in flexibility and universality.

Description

technical field [0001] The invention relates to the technical field of digital chip design, in particular to an automatic generation method of a variable bit width multiplier. Background technique [0002] The multiplier is one of the important computing components in devices such as hard-core processors, DSPs, filters, and high-performance microcontrollers. In addition to being directly used in computing units, high-performance multiplication also plays a very important role in image, voice, encryption and other signal processing fields. The structure of the multiplier is complex, the delay is large, and the operation cycle is long, and it is often on the critical path of the system. Therefore, designing and optimizing the structure of the multiplier will greatly improve the performance indicators of the entire processor system such as speed, area, and power consumption. With the emergence of high-performance computing scenarios such as machine learning and big data accele...

Claims

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Application Information

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IPC IPC(8): G06F7/523
CPCG06F7/523Y02D10/00
Inventor 邸志雄叶帅葛悦李福强周玉欣陆可承冯全源
Owner SOUTHWEST JIAOTONG UNIV
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