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Memory test array and test method thereof

A technology of memory array and test method, applied in static memory, digital memory information, instruments, etc., can solve the problem of measuring the long test time of memory elements and so on

Pending Publication Date: 2019-07-05
BEIJING ADVANCED MEMORY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In addition, in the prior art, measuring a large number of memory elements requires a long test time, so how to reduce the test time to improve test efficiency is also a technical problem to be solved

Method used

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  • Memory test array and test method thereof
  • Memory test array and test method thereof
  • Memory test array and test method thereof

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Embodiment Construction

[0028] A number of embodiments of the present invention will be disclosed below with the accompanying drawings. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. And for the sake of clarity, the size or thickness of the components may be exaggerated and not drawn according to the original size. In addition, for the sake of simplifying the illustration, some known and commonly used structures and elements will be shown in a simple and schematic manner in the illustration.

[0029] Relative terms of space are used herein, such as "below", "below", "above", "over" and so on, which is for the convenience of describing the relative relationship between one element or feature and another element or feature, such as shown in the ...

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Abstract

The invention discloses a memory test array and a test method thereof. The memory test array comprises a first memory array, a second memory array and a plurality of first common conductive pads. Thefirst memory array includes a plurality of first bit lines and a plurality of first word lines. The second memory array is adjacent to the first memory array and includes a plurality of second bit lines and a plurality of second word lines. Each first common conductive pad is provided with a first end and a second end, and the first end and the second end are coupled to the first bit line and thesecond bit line respectively or coupled to the first word line and the second word line respectively. The memory test array can effectively save the area of a memory test wafer, and enables the test process to be more efficient.

Description

technical field [0001] The invention relates to a memory test array and a test method thereof. Background technique [0002] Memory is a semiconductor device used to store data or data, and can be mainly divided into non-volatile memory and volatile memory. With the vigorous development of science and technology, the industry's demand for memory is also gradually increasing, such as high reliability, high erase and write times, fast storage speed and large capacity. Therefore, the semiconductor industry continues to strive to develop various technologies to reduce device size and increase the device density of memory. [0003] In the existing technology, such as Figure 1A As shown, a wafer includes a plurality of standard memory product chips Cp1, Cp2, and Cp4. In order to further understand the characteristics of the memory elements in the memory chip, at least one test chip (Test Chip) will be set in the wafer, such as the test chip Cp3, and it includes a plurality of m...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/56
CPCG11C29/56G11C29/56012G11C29/006G11C29/24G11C29/48G11C2029/5602G11C29/56016G11C29/50008G11C2213/79G11C13/0004G11C13/0026G11C13/0028G11C29/50012
Inventor 张雄世廖昱程蔡孟学
Owner BEIJING ADVANCED MEMORY TECH CO LTD
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